NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 573

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

Table A-3. Intel
Intel
SCB Status Word
SCB Command Word
SCB General Pointer
PORT
EEPROM Control Register
MDI Control Register
Receive DMA Byte Count
Early Receive Interrupt
Flow Control Register
PMDR
General Control
General Status
PM1 Status
PM1 Enable
PM1 Control
PM1 Timer
Processor Control
Level 2 Register
General Purpose Event 0 Status
General Purpose Event 0
Enables
SMI# Control and Enable
SMI Status Register
Alternate GPI SMI Enable
Alternate GPI SMI Status
CSR_IO_BASE set in Section 7.1.12, “CSR_IO_BASE — CSR I/O-Mapped Base Address Register (LAN Controller—
®
“CSR_MEM_BASE CSR — Memory-Mapped Base Address Register (LAN Controller—B1:D8:F0)” on page 7-256
82801DB ICH4 Datasheet
LAN CSR at CSR_IO_BASE + Offset or CSR_MEM_BASE + Offset. CSR_MEM_BASE set in Section 7.1.11,
Register Name
PMBASE set in Section 9.1.10, “PMBASE—ACPI Base Address (LPC I/F—D31:F0)” on page 9-296
LAN Control/Status Registers (CSR) may be mapped to either I/O space or memory space.
®
ICH4 Variable I/O Registers (Sheet 1 of 6)
Power Management I/O Registers at PMBASE+Offset
OBh–08h
0Fh–0Eh
01h–00h
03h–02h
07h–04h
13h–10h
17h–14h
1Ah–19h
10h–13h
2C–2Fh
3A–3Bh
00–01h
02–03h
04–07h
08–0Bh
28–2Bh
30–31h
34–35h
38–39h
Offset
1Bh
1Ch
1Dh
18h
14h
B1:D8:F0)” on page 7-257
Section 7.2.1, “System Control Block Status Word Register” on page 7-262
Section 7.2.2, “System Control Block Command Word Register” on
page 7-264
Section 7.2.3, “System Control Block General Pointer Register” on
page 7-266
Section 7.2.4, “PORT Register” on page 7-266
Section 7.2.5, “EEPROM Control Register” on page 7-267
Section 7.2.6, “Management Data Interface (MDI) Control Register” on
page 7-268
Section 7.2.7, “Receive DMA Byte Count Register” on page 7-269
Section 7.2.8, “Early Receive Interrupt Register” on page 7-269
Section 7.2.9, “Flow Control Register” on page 7-270
Section 7.2.10, “Power Management Driver (PMDR) Register” on
page 7-271
Section 7.2.11, “General Control Register” on page 7-272
Section 7.2.12, “General Status Register” on page 7-272
Section 9.8.3.1, “PM1_STS—Power Management 1 Status Register” on
page 9-354
Section 9.8.3.2, “PM1_EN—Power Management 1 Enable Register” on
page 9-356
Section 9.8.3.3, “PM1_CNT—Power Management 1 Control Register” on
page 9-357
Section 9.8.3.4, “PM1_TMR—Power Management 1 Timer Register” on
page 9-358
Section 9.8.3.5, “PROC_CNT—Processor Control Register” on page 9-358
Section 9.8.3.6, “LV2 — Level 2 Register” on page 9-359
Section 9.8.3.7, “GPE0_STS—General Purpose Event 0 Status Register” on
page 9-360
Section 9.8.3.8, “GPE0_EN—General Purpose Event 0 Enables Register” on
page 9-362
Section 9.8.3.9, “SMI_EN—SMI Control and Enable Register” on page 9-363
Section 9.8.3.10, “SMI_STS—SMI Status Register” on page 9-365
Section 9.8.3.11, “ALT_GP_SMI_EN—Alternate GPI SMI Enable Register”
on page 9-367
Section 9.8.3.12, “ALT_GP_SMI_STS—Alternate GPI SMI Status Register”
on page 9-367
Datasheet Location
Register Index
573