NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 317

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

9.2.3
9.2.4
Intel
®
82801DB ICH4 Datasheet
DMAMEM_LP—DMA Memory Low Page Registers
I/O Address:
Default Value:
Lockable:
DMACMD—DMA Command Register
I/O Address:
Default Value:
Lockable:
Bit
7:0
Bit
7:5
1:0
4
3
2
DMA Low Page (ISA Address bits [23:16]) — R/W. This register works in conjunction with the DMA
controller's Current Address Register to define the complete 24-bit address for the DMA channel.
This register remains static throughout the DMA transfer. Bit 16 of this register is ignored when in 16-
bit I/O count by words mode as it is replaced by the bit 15 shifted out from the current address
register.
Reserved. Must be 0.
DMA Group Arbitration Priority — WO. Each channel group is individually assigned either fixed or
rotating arbitration priority. At part reset, each group is initialized in fixed priority.
0 = Fixed priority to the channel group
1 = Rotating priority to the group.
Reserved. Must be 0
DMA Channel Group Enable — WO. Both channel groups are enabled following part reset.
0 = Enable the DMA channel group.
1 = Disable. Disabling channel group 4–7 also disables channel group 0–3, which is cascaded
Reserved. Must be 0.
through channel 4.
Ch. #0 = 87h; Ch. #1 = 83h
Ch. #2 = 81h; Ch. #3 = 82h
Ch. #5 = 8Bh; Ch. #6 = 89h
Ch. #7 = 8Ah;
Undefined
No
Ch. #0
Ch. #4
Undefined
No
–
–
3 = 08h;
7 = D0h
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bit
Core
WO
8 bit
Core
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