NH82801DB S L8DE Intel, NH82801DB S L8DE Datasheet - Page 308

• Manufacturer Part Number: NH82801DB S L8DE
• Manufacturer: Intel

Specifications of NH82801DB S L8DE

• Lead Free Status / RoHS Status: Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.30
9.1.31
308
GEN1_DEC—LPC I/F Generic Decode Range 1 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
15:14
15:7
Bit
6:1
Bit
13
12
11
10
0
9
8
Generic I/O Decode Range 1 Base Address (GEN1_BASE) — R/W. This address is aligned on a
128-byte boundary, and must have address lines 31:16 as 0.
NOTE: This generic decode is for I/O addresses only, not memory addresses. The size of this
Reserved
Generic Decode Range 1 Enable (GEN1_EN) — R/W.
0 = Disable.
1 = Enable the GEN1 I/O range to be forwarded to the LPC I/F
Reserved
CNF2_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 4Eh and 4Fh to the LPC interface. This range is used
CNF1_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 2Eh and 2Fh to the LPC interface. This range is used
MC_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 62h and 66h to the LPC interface. This range is used
KBC_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 60h and 64h to the LPC interface. This range is used
GAMEH_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 208h to 20Fh to the LPC interface. This range is
GAMEL_LPC_EN — R/W.
0 = Disable.
1 = Enables the decoding of the I/O locations 200h to 207h to the LPC interface. This range is
for a microcontroller.
for Super I/O devices.
for a microcontroller.
for a microcontroller.
used for a gameport.
used for a gameport.
range is 128 bytes.
E4h–E5h
00h
Yes
E6h–E7h
00h
Yes
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
R/W
16 bit
Core
R/W
16 bit
Core
®
82801DB ICH4 Datasheet