MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 1019

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

DDRJ[7:6]
DDRJ[1:0]
Reset
Reset
24.0.5.51 Port J Input Register (PTIJ)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can be used to detect
overload or short circuit conditions on output pins.
24.0.5.52 Port J Data Direction Register (DDRJ)
Read: Anytime.
Write: Anytime.
This register configures each port J pin (except PJ5-2) as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6
(RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will
not change.
The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Field
7–0
W
associated pin values.
W
R
R
1
DDRJ7
PTIJ7
Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
7
0
7
0
on PTJ or PTIJ registers, when changing the DDRJ register.
= Unimplemented or Reserved
= Unimplemented or Reserved
DDRJ6
PTIJ6
0
0
6
6
Figure 24-54. Port J Data Direction Register (DDRJ)
Figure 24-53. Port J Input Register (PTIJ)
Table 24-48. DDRJ Field Descriptions
5
0
0
5
0
0
0
0
0
0
4
4
Description
3
0
0
3
0
0
0
0
0
0
2
2
DDRJ1
PTIJ1
1
0
1
0
DDRJ0
PTIJ0
0
0
0
0