MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 720

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
is continued for another 32 lines. Upon tracing completion the breakpoint is generated, thus the breakpoint
does not occur at the tagged instruction boundary.
19.4.5.1.3
Storing with end-trigger, data is stored in the trace buffer until the final state is entered, at which point the
DBG module will become disarmed and no more data will be stored. If the trigger is at the address of a
change of flow instruction the trigger event will not be stored in the trace buffer.
19.4.5.2
The DBG module can operate in three trace modes. The mode is selected using the TRCMOD bits in the
DBGTCR register. In each mode tracing of XGATE or CPU information is possible. The source for the
trace is selected using the TSOURCE bits in the DBGTCR register. The modes are described in the
following subsections. The trace buffer organization is shown in
19.4.5.2.1
In normal mode, change of flow (COF) addresses will be stored.
COF addresses are defined as follows for the CPU:
LBRA, BRA, BSR, BGND as well as non-indexed JMP, JSR, and CALL instructions are not classified as
change of flow and are not stored in the trace buffer.
COF addresses are defined as follows for the XGATE:
Change-of-flow addresses stored include the full 23-bit address bus in the case of CPU, the 16-bit address
bus for the XGATE module and an information byte, which contains a source/destination bit to indicate
whether the stored address was a source address or destination address.
19.4.5.2.2
Loop1 mode, similarly to normal mode also stores only COF address information to the trace buffer, it
however allows the filtering out of redundant information.
The intent of loop1 mode is to prevent the trace buffer from being filled entirely with duplicate information
from a looping construct such as delays using the DBNE instruction or polling loops using
BRSET/BRCLR instructions. Immediately after address information is placed in the trace buffer, the DBG
module writes this value into a background register. This prevents consecutive duplicate address entries in
the trace buffer resulting from repeated branches.
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Source address of taken conditional branches (long, short, bit-conditional, and loop primitives)
Destination address of indexed JMP, JSR and CALL instruction.
Destination address of RTI, RTS and RTC instructions
Vector address of interrupts, except for SWI and BDM vectors
Source address of taken conditional branches
Destination address of indexed JAL instructions.
First XGATE code address, determined by the vector contained in the XGATE XGVBR register
Trace Modes
Storing with End-Trigger
Normal Mode
Loop1 Mode
MC9S12XDP512 Data Sheet, Rev. 2.21
Table
19-39.
Freescale Semiconductor