MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 1114

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
MRDS bits are readable and writable while all remaining bits read 0 and are not writable in normal mode.
The WRALL bit is writable only in special mode to simplify mass erase and erase verify operations. When
writing to the FTSTMOD register in special mode, all unimplemented/reserved bits must be written to 0.
27.3.2.4
The FCNFG register enables the Flash interrupts and gates the security backdoor writes.
1116
MRDS[1:0]
WRALL
Reset
Reset
Field
6–5
4
W
W
R
R
Margin Read Setting — The MRDS[1:0] bits are used to set the sense-amp margin level for reads of the Flash
array as shown in
Write to all Register Banks — If the WRALL bit is set, all banked FDATA registers sharing the same register
address will be written simultaneously during a register write.
0 Write only to the FDATA register bank selected using BKSEL.
1 Write to all FDATA register banks.
Flash Configuration Register (FCNFG)
0
0
0
0
7
7
Figure 27-7. Flash Test Mode Register (FTSTMOD — Special Mode)
Figure 27-6. Flash Test Mode Register (FTSTMOD —Normal Mode)
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
6
6
1 Flash array reads will be sensitive to program margin.
2 Flash array reads will be sensitive to erase margin.
Table
MRDS
MRDS
MRDS[1:0]
Table 27-8. FTSTMOD Margin Read Settings
Table 27-7. FTSTMOD Field Descriptions
27-8.
00
01
10
11
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
WRALL
0
0
0
4
4
Margin Read Setting
Description
Program Margin
Erase Margin
Normal
Normal
0
0
0
0
3
3
2
1
0
0
0
0
2
2
Freescale Semiconductor
0
0
0
0
1
1
0
0
0
0
0
0