MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 360

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.4.1.5
By enabling the PRNT bit of the TSCR1 register, the performance of the timer can be enhanced. In this
case, it is possible to set additional prescaler settings for the main timer counter and modulus down counter
and enhance delay counter settings compared to the settings in the present ECT timer.
7.4.1.6
The flags in the ECT can be cleared one of two ways:
7.4.2
The reset state of each individual bit is listed within the register description section
Map and Register
360
1. Normal flag clearing mechanism (TFFCA = 0)
2. Fast flag clearing mechanism (TFFCA = 1)
Any of the ECT flags can be cleared by writing a one to the flag.
With the timer fast flag clear all (TFFCA) enabled, the ECT flags can only be cleared by accessing
the various registers associated with the ECT modes of operation as described below. The flags
cannot be cleared via the normal flag clearing mechanism. This fast flag clearing mechanism has
the advantage of eliminating the software overhead required by a separate clear sequence. Extra
care must be taken to avoid accidental flag clearing due to unintended accesses.
— Input capture
— Output compare
— Timer counter
— Pulse accumulator A
— Pulse accumulator B
— Modulus down counter
A read from an input capture channel register causes the corresponding channel flag, CxF, to
be cleared in the TFLG1 register.
A write to the output compare channel register causes the corresponding channel flag, CxF, to
be cleared in the TFLG1 register.
Any access to the TCNT register clears the TOF flag in the TFLG2 register.
Any access to the PACN3 and PACN2 registers clears the PAOVF and PAIF flags in the
PAFLG register.
Any access to the PACN1 and PACN0 registers clears the PBOVF flag in the PBFLG register.
Any access to the MCCNT register clears the MCZF flag in the MCFLG register.
Reset
Precision Timer
Flag Clearing Mechanisms
Definition”) which details the registers and their bit-fields.
MC9S12XDP512 Data Sheet, Rev. 2.21
(Section 7.3, “Memory
Freescale Semiconductor