MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 255
MC9S12XDT512CAA
Manufacturer Part Number
MC9S12XDT512CAA
Description
Manufacturer
Freescale
Datasheet
1.MC9S12XDT512CAA.pdf
(1348 pages)
Specifications of MC9S12XDT512CAA
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
40MHz
Interface Type
CAN/I2C/SCI/SPI
Total Internal Ram Size
32KB
# I/os (max)
59
Number Of Timers - General Purpose
12
Operating Supply Voltage (typ)
2.5/5V
Operating Supply Voltage (max)
2.75/5.5V
Operating Supply Voltage (min)
2.35/3.15V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Program Memory Type
Flash
Program Memory Size
512KB
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12XDT512CAA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MC9S12XDT512CAAR
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CSL
Operation
n = RS or IMM4
Shifts the bits in register RD n positions to the left. The lower n bits of the register RD become filled with
the carry flag. The carry flag will be updated to the bit contained in RD[16-n] before the shift for n > 0.
n can range from 0 to 16.
In immediate address mode, n is determined by the operand IMM4. n is considered to be 16 in IMM4 is
equal to 0.
In dyadic address mode, n is determined by the content of RS. n is considered to be 16 if the content of RS
is greater than 15.
CCR Effects
Code and CPU Cycles
Freescale Semiconductor
N:
Z:
V:
C:
CSL RD, #IMM4
CSL RD, RS
N
Set if bit 15 of the result is set; cleared otherwise.
Set if the result is $0000; cleared otherwise.
Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RD[15]
Set if n > 0 and RD[16-n] = 1; if n = 0 unaffected.
Z
V
Source Form
old
^ RD[15]
C
new
C
Address
MC9S12XDP512 Data Sheet, Rev. 2.21
Logical Shift Left with Carry
Mode
IMM4
DYA
RD
0
0
n
0
0
0
0
0
0
1
1
Machine Code
RD
RD
C
C
n bits
RS
IMM4
C
C
Chapter 6 XGATE (S12XGATEV2)
1
1
0
0
0
CSL
1
1
0
0
Cycles
P
P
255
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