MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 552

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 13 Periodic Interrupt Timer (S12PIT24B4CV1)
Whenever a 16-bit timer counter and the connected 8-bit micro timer counter have counted to zero, the
PITLD register is reloaded and the corresponding time-out flag PTF in the PIT time-out flag (PITTF)
register is set, as shown in
micro timer load (PITMTLD) registers and the bus clock f
For example, for a 40 MHz bus clock, the maximum time-out period equals:
The current 16-bit modulus down-counter value can be read via the PITCNT register. The micro timer
down-counter values cannot be read.
The 8-bit micro timers can individually be restarted by writing a one to the corresponding force load micro
timer PFLMT bits in the PIT control and force load micro timer (PITCFLMT) register. The 16-bit timers
can individually be restarted by writing a one to the corresponding force load timer PFLT bits in the PIT
forceload timer (PITFLT) register. If desired, any group of timers and micro timers can be restarted at the
same time by using one 16-bit write to the adjacent PITCFLMT and PITFLT registers with the relevant
bits set, as shown in
13.4.2
Each time-out event can be used to trigger an interrupt service request. For each timer channel, an
individual bit PINTE in the PIT interrupt enable (PITINTE) register exists to enable this feature. If PINTE
552
Note 1. The PTF flag clearing depends on the software
16-Bit Force Load
PITCNT Register
8-Bit Force Load
Timer Counter
time-out period = (PITMTLD + 1) * (PITLD + 1) / f
256 * 65536 * 25 ns = 419.43 ms.
8-Bit Micro
PTF Flag
Bus Clock
PITTRIG
Interrupt Interface
1
Figure
00
0
2
Figure
13-20.
0001
Time-Out Period
Figure 13-20. PIT Trigger and Flag Signal Timing
1
0
13-20. The time-out period is a function of the timer load (PITLD) and
MC9S12XDP512 Data Sheet, Rev. 2.21
2
0000
1
0
2
0001
1
0
BUS
2
0000
BUS
:
1
.
2
Time-Out Period
0001
1
After Restart
0
2
0000
1
Freescale Semiconductor
0
2
0001
1
0
2