L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 11

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

September 2007
Functional Description
Low-Power Modes
Hardware Powerdown Mode
In Hardware Powerdown, all PHY functions (analog and
digital) are disabled. During Hardware Powerdown,
SYS_CLK is not available and the MII registers are not
accessible. This is the lowest power mode for the ET1011C.
Hardware Powerdown is entered when the LPED_EN_N and
SYS_CLK_EN_N pins are high (deasserted), and either the
COMA signal is high (asserted) or the RESET_N signal is
driven low (asserted).
Low-Power Energy-Detect (LPED) Mode
In LPED mode, the PHY is in a low power state but still
monitors the cable (MDI interface) for energy. If energy is
detected, the MDINT_N pin is asserted. During LPED
mode, SYS_CLK is not available and the MII registers are
not accessible. The host system monitors the MDINT_N pin
and then places the PHY into a regular operating mode in
response to the interrupt. LPED mode is entered when the
LPED_EN_N pin is low (asserted), SYS_CLK_EN_N pin is
high (deasserted), and either the COMA signal is high
(asserted) or the RESET_N signal is driven low (asserted).
At exit from Hardware Powerdown or LPED modes, the
ET1011C does the following:
n
n
n
n
Standby Powerdown Mode
In Standby Powerdown, most PHY functions (analog and
digital) are disabled but the PLL is still running. During
Standby Powerdown, SYS_CLK is available and the MII
registers are not accessible. Standby Powerdown mode is
entered when the LPED_EN_N pin is high (deasserted),
SYS_CLK_EN_N pin is low (asserted), and either the
COMA signal is high (asserted) or the RESET_N signal is
driven low (asserted).
Standby Powerdown with Low-Power Energy-Detect
(LPED) Mode
LSI Corporation
Initializes all analog circuits including the PLL.
Initializes all digital logic and state machines.
Reads and latches the PHY address pins.
Initializes all MII registers to their default values (H/W
configuration pins are reread).
(continued)
This powerdown mode is a combination of Standby Power-
down mode and LPED mode. The PLL is running and the
PHY monitors the cable (MDI interface) for energy. If
energy is detected, the MDINT_N pin is asserted. During
this mode, SYS_CLK is available and the MII registers are
not accessible. The host system monitors the MDINT_N pin
and then places the PHY into a regular operating mode in
response to the interrupt. This mode is entered when the
LPED_EN_N pin is low (asserted), SYS_CLK_EN_N pin is
low (asserted), and either the COMA signal is high
(asserted) or the RESET_N signal is driven low (asserted).
At exit from Standby Powerdown or Standby Powerdown
with LPED, the ET1011C does the following:
n
n
n
n
Software Powerdown Mode
Software powerdown is entered when bit 11 of the control
register (MII register address 0, bit 11) is set. In software
powerdown, all PHY functions except the serial manage-
ment interface and clock circuitry are disabled. The MII reg-
isters can be read or written. If the system clock output is
enabled (MII register address 22, bit 4), the 125 MHz system
clock will still be available for use by the MAC on pin
SYS_CLK.
At exit from software powerdown, the ET1011C initializes
all digital logic and state machines only. NOTE: The H/W
configuration pins and the PHY address pins are not re-read
and the MII registers are not reset to their default values.
These operations are only done during reset or recovery from
hardware powerdown.
Wake-On-LAN Powerdown Mode
ACPI power consumption compliant Wake-On-LAN mode
is implemented on the ET1011C by using the IEEE standard
MII registers to put the PHY into 10Base-T or 100Base-TX
modes. Clearing the advertisement of 1000Base-T (MII reg-
ister address 9, bits 8, 9) and setting the desired 10Base-T
and 100Base-TX advertisement (MII register address 4, bits
5—8) activates this feature. This must be followed by an
autonegotiation restart via the control register (MII register
address 0, bit 9).
Initializes all analog circuits excluding the PLL.
Initializes all digital logic and state machines.
Reads and latches the PHY address pins.
Initializes all MII registers to their default values (H/W
configuration pins are reread).
Gigabit Ethernet Transceiver
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