L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 33

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

September 2007
LSI Corporation
Hardware Interfaces
Clocking and Reset
Table 13. Clocking and Reset
SYS_CLK
Pin Name
RESET_N
CLK_IN
XTAL_1
XTAL_2
COMA
128-Pin
TQFP
Pin #
31
31
32
94
34
25
(continued)
MLCC
84-Pin
Pin #
22
22
23
57
24
—
MLCC
68-Pin
Pin #
16
17
50
16
18
12
Reference Clock
Input
Reference
Crystal Input
Reference
Crystal Input
System Clock
Reset
Hardware
Powerdown
Pin Description
Connect this signal to a 25 MHz clock input
(CLK_IN will only accept a 2.5V signal) or a 25
MHz ± 50 ppm tolerance crystal (XTAL_1).
Connect this signal to a 25 MHz ± 50 ppm tolerance
crystal. Float this signal if an external clock is used
(CLK_IN).
Use this signal to supply a 125 MHz clock to the
MAC.
By default, the SYS_CLK output is disabled. The
SYS_CLK output can be enabled by asserting the
SYS_CLK_EN_N pin or via the management inter-
face.
Drive RESET_N low for 20 μs to initiate a hardware
reset. The ET1011C completes all reset operations
within 5 ms of this signal returning to a high state.
The configuration pins and the physical address con-
figuration are read during a hardware reset.
See Low Power Modes on page 11 for additional
information.
Drive COMA high to initiate a hardware power-
down. The ET1011C completes all reset operations
within 5 ms of this signal returning to a low state.
All hardware functions are disabled during a hard-
ware powerdown.
The configuration pins and the physical address con-
figuration are read during a hardware powerdown.
See Low Power Modes on page 11 for additional
information.
Functional Description
Gigabit Ethernet Transceiver
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