L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 34

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Gigabit Ethernet Transceiver
Hardware Interfaces
JTAG
The ET1011C has a standard IEEE 1149.1 JTAG test interface. The interface provides extensive test and diagnostics capabil-
ity. It contains internal circuitry that allows the device to be controlled through the JTAG port to provide on-chip, in-circuit
emulation.
The JTAG interface is a bidirectional serial interface with its own reset strobe (TRST_N). The reset strobe can be used inde-
pendently to reset the JTAG state machine but must be used during a power-on reset (see Reset Timing on page 78).
Table 14. JTAG Test Interface
Regulator Control
The ET1011C has two on-chip regulator controllers. This allows the device to be powered from a single supply, either 3.3 V or
2.5 V. The on-chip regulator control circuits provide output control voltages that can be used to control two external transistors
and thus provide regulated 1.0 V and 2.5 V supplies.
Table 15. Regulator Control Interface
34
CTRL_1V0
CTRL_2V5
Pin Name
Pin Name
TRST_N
TDO
TCK
TMS
TDI
128-Pin
TQFP
Pin #
128-Pin
TQFP
Pin #
16
17
10
15
14
79
78
MLCC
84-Pin
(continued)
Pin #
MLCC
84-Pin
14
15
13
12
Pin #
5
47
46
MLCC
68-Pin
Pin #
MLCC
68-Pin
Pin #
7
8
2
6
5
40
39
Test Data Input
Test Data
Output
Test Clock
Test Mode
Select
Test Reset
(JTAG Reset)
Pin Description
Regulator
Control for
1.0 V
Regulator
Control for
2.5 V
Description
Pin
This signal is the JTAG serial input. All instructions and
scanned data are input using this pin. This pin has an
internal pull-up resistor.
This signal is the JTAG serial output. Scanned data and
status bits are output using this pin. This pin has an inter-
nal pull-up resistor.
This signal is the JTAG serial shift clock. It clocks all of
the data that passes through the port on TDI and TDO.
This pin has an internal pull-up resistor.
This signal is the JTAG test mode control. This pin has an
internal pull-up resistor.
This signal is active-low and causes the JTAG TAP con-
troller to enter the reset state. This pin has an internal
pull-down resistor.
This is the regulator output control voltage for the
1.0 V supply. It is used to control an external transis-
tor and thus provide a regulated 1.0 V supply.
This is the regulator output control voltage for the
2.5 V supply. It is used to control an external transis-
tor and thus provide a regulated 2.5 V supply.
Functional Description
Functional Description
September 2007
LSI Corporation