L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 4

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Contents
Gigabit Ethernet Transceiver
Figure
Figure 1. ET1011C Block Diagram...................................... 5
Figure 2. Loopback Functionality ........................................ 9
Figure 3. Digital Loopback................................................... 9
Figure 4. Replica and Line Driver Analog Loopback ........ 10
Figure 5. External Cable Loopback.................................... 10
Figure 6. Pin Diagram for ET1011C in
Figure 7. Pin Diagram for ET1011C in
Figure 8. Pin Diagram for ET1011C in
Figure 9. ET1011C Gigabit Ethernet Card
Figure 10. GMII MAC-PHY Signals ................................. 22
Figure 11. RGMII MAC-PHY Signals............................... 23
Figure 12. MII Signals........................................................ 24
Figure 13. Ten-Bit Interface ............................................... 25
Figure 14. Reduced Ten-Bit Interface ................................ 26
Figure 15. GMII 1000Base-T Transmit Timing ................. 67
Figure 16. GMII 1000Base-T Receive Timing .................. 68
4
128-Pin TQFP Package (Top View).............. 12
84-Pin MLCC Package (Top View) .............. 13
68-Pin MLCC Package (Top View) .............. 14
Block Diagram .............................................. 21
Table of Contents
Page
Contents
Figure 17. RGMII 1000Base-T Transmit Timing—
Figure 18. RGMII 1000Base-T Transmit Timing—
Figure 19. RGMII 1000Base-T Receive Timing—
Figure 20. RGMII 1000Base-T Receive Timing—
Figure 21. MII 100Base-TX Transmit Timing....................73
Figure 22. MII 100Base-TX Receive Timing .....................74
Figure 23. MII 10Base-T Transmit Timing ........................75
Figure 24. MII 10Base-T Receive Timing ..........................76
Figure 25. Serial Management Interface Timing ................77
Figure 26. Reset Timing......................................................78
Figure 27. Clock Timing .....................................................79
Figure 28. JTAG Timing .....................................................80
Figure
(continued)
Trace Delay....................................................69
Internal Delay ................................................70
Trace Delay....................................................71
Internal Delay ................................................72
September 2007
LSI Corporation
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