L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 27

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

September 2007
LSI Corporation
Hardware Interfaces
Management Interface
Serial Management Interface
The MII management interface (MI) provides a simple, two-wire serial interface between the MAC and the PHY to allow
access to control and status information in the internal registers of the ET1011C. The interface is compliant with IEEE 802.3
clause 22 and is compatible with the clause 45.3, enabling the two systems to co-exist on the same MDIO bus.
Management Frame Structure
Frames transmitted on the MI have the following structure.
Table 8. Management Frame Structure
n
n
n
n
n
n
n
n
Read
Write
PRE (preamble): At the beginning of each transaction, the MAC may send a sequence of 32 contiguous logic one bits on
MDIO with 32 corresponding cycles on MDC to provide the PHY with a pattern that it can use to establish synchronization.
The ET1011C supports MF preamble suppression, and thus the MAC may initiate management frames with the ST (start of
frame) pattern.
ST (start of frame): The start of frame is indicated by a <01> pattern. This pattern ensures transitions from the default logic
one line state to zero and back to one. When a clause 45 start of frame <00> is received, the frame is ignored.
OP (operation code): The operation code for a read transaction is <10>, while the operation code for a write transaction is
<01>.
PHYAD (PHY address): The PHY address is 5 bits. The first PHY address bit transmitted and received is the MSB of the
address. Only the PHY that is addressed will respond to the MI operation.
REGAD (register address): The register address is 5 bits. The first register address bit transmitted and received is the MSB
of the address.
TA (turnaround): The turnaround time is a 2-bit time spacing between the register address field and the data field of a man-
agement frame to avoid contention during a read transaction. For a read transaction, the PHY remains in a high-impedance
state for the first bit time of the turnaround and drives a zero bit during the second bit time of the turnaround. During a write
transaction, the PHY expects a one for the first bit time of the turnaround and a zero for the second bit time of the turn-
around.
DATA (data): The data field is 16 bits. The first data bit transmitted and received is the MSB of the register being addressed.
IDLE (idle condition): The IDLE condition on MDIO is a high-impedance state, and the ET1011C internal pull-up resistor
will pull the MDIO line to logic one.
1. . . 1
1 . . . 1
PRE
01
01
ST
(continued)
10
01
OP
aaaaa
aaaaa
PHYAD
rrrrr
rrrrr
REGAD
ZO
10
TA
d . . . d
d . . . d
DATA
Gigabit Ethernet Transceiver
Z
Z
IDLE
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