L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 53

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

September 2007
LSI Corporation
Register Functions/Settings
Table 43. PHY Control Register—Address 23
1. This bit is only valid when the PHY is in PHY standby mode (26.15 = 1) and after the IP phone detect enable bit (23.14) has been set and has self-cleared
2. Setting this bit enables the automatic IP phone detection algorithm and clears the IP phone detected bit (23.15). Diagnostics must be enabled (18.2 = 1),
3. This bit sets the cable diagnostics mode. The default is link analysis mode wherein the PHY brings up a link with a remote partner. For analysis of cable
4. This bit allows independent control over TXC and RXC DLL delay. Settings are shown below:
to indicate that the IP phone detection algorithm has completed.
cable diagnostic TDR mode must be selected (23.13 = 0), and the PHY must be in PHY standby mode (26.15 = 1) to do IP phone detection. IP phone detect
enable self-clears when the IP phone detection algorithm is complete, the result is then indicated in IP phone detected.
faults, the PHY can be put in TDR mode. In TDR mode, the PHY will not respond to link pulses from a remote link partner and will not bring up a link.
12:11
10:7
Bit
15
14
13
6
5
4
3
2
1
0
22.2:0
10x
11x
10x
11x
RGMII Mode
IP Phone Detected
IP Phone Detect
Enable
Cable Diagnostic
Mode
Automatic Speed
Downshift Attempts
Before Downshift
Reserved
Alternative RGMII
TXC DLL Delay
Jabber
(10Base-T)
SQE
(10Base-T)
TP_LOOPBACK
(10Base-T)
Preamble Genera-
tion Enable
Reserved
Force Interrupt
23.6
0
0
1
1
Name
TXC
0 ns
2 ns
2 ns
0 ns
Delay
1 = IP phone detected.
0 = IP phone not detected.
1 = Enable automatic IP phone detect.
0 = Disable automatic IP phone detect.
1 = Link analysis mode.
0 = TDR mode.
00 = 1.
01 = 2.
10 = 3.
11 = 4.
1 = TXC DLL delay in RGMII mode is opposite of RXC.
0 = TXC DLL delay in RGMII mode is same as RXC.
1 = Disable jabber.
0 = Normal operation.
1 = Enable heartbeat.
0 = Disable heartbeat.
1 = Disable TP loopback during half-duplex.
0 = Normal operation.
1 = Enable preamble generation for 10Base-T.
0 = Disable preamble generation for 10Base-T.
1 = Assert MDINT_N pin.
0 = Deassert MDINT_N pin.
RXC
(continued)
0 ns
2 ns
0 ns
2 ns
RGMII (trace delay).
RGMII (TXC and RXC DLL delay).
RGMII (TXC DLL delay).
RGMII (RXC DLL delay).
PHY Control Register
Description
Description
—
—
Gigabit Ethernet Transceiver
Type
R/W,
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO
SC
—
—
See Note 1,
Table 10,
page 30.
Default
11
—
—
0
0
1
0
0
1
1
0
Notes
—
—
—
—
—
—
—
—
1
2
3
4
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