L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 29

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

September 2007
LSI Corporation
Hardware Interfaces
Configuration Interface
The hardware configuration pins listed in Table 10 initialize the ET1011C at power-on and reset. The configuration is latched
during initialization and stored. These pins set the default value of their corresponding MII register bits.
Some configuration inputs are shared with LED pins. The hardware configuration and LED pins are read on initial powerup of
the ET1011C, during a hardware reset and during recovery from hardware powerdown. The logic value at the pin is sensed
and latched. After RESET_N has been deasserted (raised high), the shared configuration pins become outputs that are used to
drive LEDs. (For details on sharing LED and configuration pins, refer to the application note, TruePHY ET1011 Gigabit
Ethernet PHY Design and Layout Guide.)
Table 10. Configuration Signals
SYS_CLK_EN_N
SPEED_1000
LPED_EN_N
Pin Name
PAUSE
PRES
128-Pin
TQFP
Pin #
82
85
15
16
87
(continued)
MLCC
84-Pin
Pin #
49
50
13
14
51
MLCC
68-Pin
Pin #
42
43
44
6
7
Description
Speed 1000 The SPEED_1000 configuration pin sets the
Low Power
SYS_CLK
Detection
Precision
Resistor
Enable
Energy
Enable
Pause
Pin
default advertised speed. The deassertion of
SPEED_1000 disables advertisement of the
1000Base-T to the remote end. The default is to
advertise all three speeds.
This input sets the pause mode. If PAUSE is
asserted, full-duplex pause and asymmetric
pause operation are advertised. 0 = Don't adver-
tise pause (default).1 = Advertise full-duplex
pause and asymmetric pause.
Enables the system clock.
If SYS_CLK_EN_N is asserted when RESET_N
is low, SYS_CLK will be enabled and will con-
tinue to be generated while RESET_N is low. If
SYS_CLK_EN_N is not asserted when
RESET_N is low, then SYS_CLK is disabled.
0 = SYS_CLK enabled.
1 = SYS_CLK disabled (default).
See Low Power Modes on page 11 for additional
information.
LPED_EN_N enables the low-power energy-
detect (LPED) mode when COMA is asserted.
See Low Power Modes on page 11 for additional
information.
When the PHY is in LPED mode, it can wake the
MAC/controller (instead of Magic Packet) by
asserting the MDINT_N pin to indicate the pres-
ence of cable energy.
0 = Low-power energy-detect mode enable.
1 = Low-power energy-detect mode disabled
(default).
Connect a 1.0 kΩ precision resistor to ground to
set termination for all digital I/Os.
Functional Description
Gigabit Ethernet Transceiver
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