L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 24

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Gigabit Ethernet Transceiver
Hardware Interfaces
Media-Independent Interface (128-Pin TQFP and
84-Pin MLCC Only)
The MII is fully compliant with IEEE 802.3 clause 22. The
MII interface mode is selected by setting the hardware con-
figuration pins MAC_IF_SEL[2:0] = 000.
In 100Base-TX and 10Base-T mode, the RXD[7:4] pins are
driven low by the ET1011C and the TXD[7:4] pins are
ignored. They should not be left floating but should be set
either high or low. In the MII interface mode, the GTX_CLK
pin may be held low.
An alternative to the standard MII is provided when operat-
ing in 10Base-T or 100Base-TX mode by
setting hardware configuration pins
MAC_IF_SEL[2:0] = 010. In this alternative interface, the
MAC provides a reference clock at 2.5 MHz or
Table 5. MII Interface (100Base-TX and 10Base-T) (128-Pin TQFP and 84-Pin MLCC Only)
24
GTX_CLK
Pin Name
TXD[3:0]
RXD[3:0]
RX_CLK
TX_CLK
RX_DV
TX_EN
RX_ER
TX_ER
COL
CRS
105, 106,
127, 126
107, 108
128-Pin
TQFP
3, 128,
Pin #
121
124
125
113
110
109
118
116
115
83, 82, 81,
65, 66, 67,
MLCC
84-Pin
Pin #
(continued)
75
77
78
79
80
72
70
69
68
74
73
Transmit error The MAC drives this signal high to indicate a transmit coding error.
Collision
detect
transmit clock
Receive clock In 100Base-TX mode, the ET1011C generates 25 MHz reference clocks
Transmit data
Receive error The ET1011C drives RX_ER to indicate that an error was detected in the
Carrier sense The carrier sense signal (CRS) of the MAC interface is asserted by the
Receive data
Receive data
Description
Alternate
Transmit
Transmit
enable
clock
valid
Pin
bits
bits
In 100Base-TX mode, the ET1011C generates 25 MHz reference clocks
and in 10Base-T mode provides 2.5 MHz reference clocks.
MAC_IF_SEL[2:0] = 000—this is default behavior.
In 100Base-TX mode, the MAC generates the 25 MHz reference clock and
in 10Base-T mode provides a 2.5 MHz reference clock. MAC_IF_SEL[2:0]
= 010.
The MAC drives this signal high to indicate that data is available on the
transmit data bus.
The MAC transmits data synchronized with TX_CLK to the ET1011C for
transmission on the media-dependent (transformer) interface.
and in 10Base-T mode provides 2.5 MHz reference clocks.
frame that was received and is being transmitted to the MAC.
The ET1011C drives RX_DV to indicate that it is sending recovered and
decoded data to the MAC.
The ET1011C transmits data synchronized with RX_CLK to the MAC.
ET1011C whenever the receive medium is nonidle. In half-duplex mode,
CRS may also be asserted when the transmit medium is nonidle. The CRS
may be enabled on transmit in half-duplex mode by writing to the PHY
configuration register, address 22, bit 15.
In 10Base-T, 100Base-TX, and 1000Base-T half-duplex modes, COL is
asserted when both transmit and receive media are nonidle.
25 MHz at the GTX_CLK pin. The ET1011C then uses a
FIFO to resynchronize data presented synchronously with
this reference clock.
Functional Description
MAC
Figure 12. MII Signals
RXD[3:0]
RX_CLK
TX_CLK
TXD[3:0]
RX_ER
RX_DV
TX_ER
TX_EN
COL
CRS
PHY
September 2007
LSI Corporation