L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 52

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Gigabit Ethernet Transceiver
Register Description
Register Functions/Settings
Table 42. PHY Configuration Register—Address 22
1. If automatic speed downshift is enabled and the PHY fails to autonegotiate at 1000Base-T, the PHY will fall back to attempt connection at 100Base-TX
2. Value is read from inversion of SYS_CLK_EN_N at reset.
3. For the 68-pin MLCC, only RGMII and RTBI modes/options are supported.
Register Description
52
13:12
11:10
and, subsequently, 10Base-T. This cycle will repeat. If the link is broken at any speed, the PHY will restart this process by reattempting connection at the
highest possible speed (e.g., 1000Base-T).
Bit
2:0
15
14
9
8
7
6
5
4
3
CRS Transmit Enable
Reserved
Transmit FIFO depth
(1000Base-T)
Automatic Speed
Downshift Mode
TBI Detect Select
TBI Rate Select
Alternate Next-Page
Group MDIO Mode
Enable
Transmit Clock Enable 1 = Enable output of 1000Base-T transmit clock
System Clock Enable
Reserved
MAC Interface Mode
Select
Name
(continued)
(continued)
(continued)
1 = Enable CRS on transmit in half-duplex mode.
0 = Disable CRS on transmit.
00 = ±8.
01 = ±16.
10 = ±24.
11 = ±32.
00 = Disable automatic speed downshift.
10 = 100Base-TX downshift enabled.
x1 = 100Base-TX and 10Base-T enabled.
1 = CRS pin outputs comma detect.
0 = CRS pin outputs link status detect
1 = Output 125 MHz clock on RX_CLK while
COL is held low (full rate).
0 = Output even/odd clocks on RX_CLK/COL
1 = Enables manual control of 1000Base-T next
pages only.
0 = Normal operation of 1000Base-T next page
exchange
1 = Enable group MDIO mode.
0 = Disable Group MDIO mode.
(TX_CLK pin).
0 = Disable output.
1 = Enable output of 125 MHz reference clock
(SYS_CLK pin).
0 = Disable output of 125 MHz reference clock.
000 = GMII/MII.
001 = TBI.
010 = GMII/MII clocked by GTX_CLK instead of
TX_CLK.
011 = Reserved.
100 = RGMII (trace delay).
101 = RTBI (trace delay).
110 = RGMII (DLL delay).
111 = RTBI (DLL delay).
PHY Configuration Register
Description
—
—
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
SYS_CLK_EN_N
See bit 23.6 (next
Note 1, Table 10,
page) and
page 30.
Default
—
01
11
—
September 2007
0
0
0
0
0
0
LSI Corporation
Notes
—
—
—
—
—
—
—
—
—
1
2
3