L-ET1011C2-CI-D LSI, L-ET1011C2-CI-D Datasheet - Page 2

• Manufacturer Part Number: L-ET1011C2-CI-D
• Manufacturer: LSI

Specifications of L-ET1011C2-CI-D

• Number Of Receivers: 1
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / Rohs Status: Compliant

Contents
Gigabit Ethernet Transceiver
Features................................................................................. 1
Introduction .......................................................................... 1
Functional Description ......................................................... 5
Pin Information................................................................... 12
Cable Diagnostics............................................................... 36
Register Description ........................................................... 37
Electrical Specifications ..................................................... 62
Timing Specification .......................................................... 67
2
Oversampling Architecture............................................... 5
Automatic Speed Downshift ............................................. 5
Transmit Functions ........................................................... 6
Receive Functions............................................................. 6
Autonegotiation ................................................................ 7
Carrier Sense (128-Pin TQFP and
Link Monitor..................................................................... 8
LEDs ................................................................................. 8
Regulator Control ............................................................. 8
Resetting the ET1011C ..................................................... 8
Loopback Mode ................................................................ 9
Digital Loopback .............................................................. 9
Analog Loopback............................................................ 10
Low-Power Modes.......................................................... 11
Pin Diagram, 128-Pin TQFP .......................................... 12
Pin Diagram, 84-Pin MLCC ........................................... 13
Pin Diagram, 68-Pin MLCC .......................................... 14
Pin Descriptions, 128-Pin TQFP, 84-Pin MLCC,
MAC Interface ................................................................ 22
Management Interface .................................................... 27
Configuration Interface................................................... 29
LEDs Interface ................................................................ 31
Media-Dependent Interface:
Clocking and Reset ......................................................... 33
JTAG............................................................................... 34
Regulator Control ........................................................... 34
Power, Ground, and No Connect .................................... 35
Register Address Map..................................................... 37
Register Functions/Settings ............................................ 38
Absolute Maximum Ratings ........................................... 62
Recommended Operating Conditions ............................. 62
Device Electrical Characteristics .................................... 63
GMII 1000Base-T Transmit Timing
GMII 1000Base-T Receive Timing
RGMII 1000Base-T Transmit Timing ............................ 69
RGMII 1000Base-T Receive Timing ............................. 71
MII 100Base-TX Transmit Timing................................. 73
MII 100Base-TX Receive Timing ................................. 74
MII 10Base-T Transmit Timing ..................................... 75
84-Pin MLCC Only) ..................................................... 7
and 68-Pin MLCC....................................................... 15
Transformer Interface ................................................. 32
(128-Pin TQFP and 84-Pin MLCC Only)................... 67
(128-Pin TQFP and 84-Pin MLCC Only)................... 68
Table of Contents
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Contents
Package Diagram, 128-Pin TQFP ......................................81
Package Diagram, 84-Pin MLCC ......................................82
Package Diagram, 68-Pin MLCC ......................................83
Ordering Information .........................................................84
Table
Table 1. ET1011C Device Signals
Table 2. Multiplexed Signals on the ET1011C .................. 20
Table 3. GMII Signal Description (1000Base-T
Table 4. RGMII Signal Description
Table 5. MII Interface (100Base-TX and
Table 6. Ten-Bit Interface (1000Base-T)
Table 7. RTBI Signal Description
Table 8. Management Frame Structure .............................. 27
Table 9. Management Interface.......................................... 28
Table 10. Configuration Signals......................................... 29
Table 11. LED ................................................................... 31
Table 12. Transformer Interface Signals ............................ 32
Table 13. Clocking and Reset ............................................ 33
Table 14. JTAG Test Interface............................................ 34
Table 15. Regulator Control Interface................................ 34
Table 16. Supply Voltage Combinations............................ 35
Table 17. Power, Ground, and No Connect........................ 35
Table 18. Cable Diagnostic Functions ............................... 36
Table 19. Register Address Map ........................................ 37
Table 20. Register Type Definition .................................... 37
Table 21. Control Register—Address 0 ............................. 38
Table 22. Status Register—Address 1................................ 39
Table 23. PHY Identifier Register 1—Address 2 ...............40
Table 24. PHY Identifier Register 2—Address 3 ...............40
Table 25. Autonegotiation Advertisement Register—
Table 26. Autonegotiation Link Partner Ability
Table 27. Autonegotiation Expansion Register
MII 10Base-T Receive Timing........................................76
Serial Management Interface Timing..............................77
Reset Timing ...................................................................78
Clock Timing...................................................................79
JTAG Timing ..................................................................80
by Interface, 128-Pin TQFP, 84-Pin
and 68-Pin MLCC........................................... 15
Mode) (128-pin TQFP and
84-pin MLCC only) ........................................ 22
(1000Base-T Mode)........................................ 23
10Base-T) (128-Pin TQFP and
84-Pin MLCC Only) ....................................... 24
(128-Pin TQFP and 84-Pin MLCC Only)....... 25
(1000Base-T Mode) ....................................... 26
Address 4 .........................................................41
Register—Address 5 ....................................... 42
—Address 6 .................................................... 43
September 2007
LSI Corporation
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