DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 18

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

4 0 Refresh Options
4 3 EXTENDING REFRESH
The programmed number of periods of CLK that refresh
RASs are asserted can be extended by one or multiple peri-
ods of CLK Only the all RAS (with or without error scrub-
bing) type of refresh can be extended To extend a refresh
cycle the input extend refresh EXTNDRF must be assert-
ed before the positive edge of CLK that would have negated
all the RAS outputs during the refresh cycle and after the
positive edge of CLK which starts all RAS outputs during the
refresh as shown in Figure 13 This will extend the refresh to
the next positive edge of CLK and EXTNDRF will be sam-
pled again The refresh cycle will continue until EXTNDRF is
sampled low on a positive edge of CLK
4 4 CLEARING THE REFRESH ADDRESS COUNTER
The refresh address counter can be cleared by asserting
RFSH while DISRFSH is negated as shown in Figure 14a
This can be used prior to a burst refresh of the entire memo-
FIGURE 13 Extending Refresh with the Extend Refresh (EXTNDRF) Input
FIGURE 15 Clearing the Refresh Request Clock Counter
FIGURE 14b Clearing the Refresh Counter during Burst
(Continued)
FIGURE 14a Clearing the Refresh Address Counter
18
ry array By asserting RFSH one period of CLK before
DISRFSH is asserted and then keeping both inputs assert-
ed the DP8520A 21A 22A will clear the refresh address
counter and then perform refresh cycles separated by the
programmed value of precharge as shown in Figure 14b An
end-of-count signal can be generated from the Q VRAM
address outputs of the DP8520A 21A 22A and used to ne-
gate RFSH
4 5 CLEARING THE REFRESH REQUEST CLOCK
The refresh request clock can be cleared by negating
DISRFSH and asserting RFSH for 500 ns one period of the
internal 2 MHz clock as shown in Figure 15 By clearing the
refresh request clock the user is guaranteed that an inter-
nal refresh request will not be generated for approximately
15 s one refresh clock period from the time RFSH is neg-
ated This action will also clear the refresh address counter
TL F 9338 – 20
TL F 9338 – 21
TL F 9338– 19
TL F 9338– 22