DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 36

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

8 0 RAS and CAS Configuration Modes
8 5 PAGE BURST MODE
In a static column page or burst mode system the least
significant bits must be tied to the column address in order
to ensure that the page burst accesses are to sequential
memory addresses as shown in Figure 44 In a nibble mode
system the two least significant address bits (A2 A3) must
be tied to the highest row and column address inputs (de-
pends on VRAM size) to ensure that the toggling bits of
nibble mode VRAMs are to sequential memory addresses
Assume that the least significant address bits are used for byte addressing Given a 32-bit system A0 A1 would be
used for byte addressing
X
Assuming 1 M-bit Vrams are being used
Addresses
e
See table below for row column
Address
Address
Column
Row
DON’T CARE the user can do as he pleases
B0
B1
R9 C9
Nibble Mode
C0– 8
FIGURE 44 Page Static Column Nibble Mode System
A4
A5
e
X
e
A2 A3
X
bank address bit map A0 A1 are used for byte addressing in this example
256 Bits Page
C0– 7
C8– 10
A10
A11
e
X
A2– 9
e
X
Page Mode Static Column Mode Page Size
C0–8
36
512 Bits Page
C9 10
(Continued)
The ECAS inputs may then be toggled with the DP8520A
21A 22A’s address latches in fall-through mode while
AREQ is asserted The ECAS inputs can also be used to
select individual bytes When using nibble mode VRAMS
the third and fourth address bits can be tied to the bank
select inputs to perform memory interleaving In page or
static column modes the two address bits after the page
size can be tied to the bank select inputs to select a new
bank if the page size is exceeded
A11
A12
e
X
A2–10
e
X
1024 Bits Page
C0 –9
C10
A12
A13
e
X
e
A2–11
X
C0 –10
2048 Bits Page
A13
A14
e
X
A2–12
TL F 9338– 95