DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 37

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

9 0 Programming and Resetting
The DP8520A 21A 22A must be programmed by one of
two possible programming sequences before it can be used
After power up the DP8520A 21A 22A must be externally
reset (see External Reset) before programming After pro-
gramming the DP8520A 21A 22A enters a 60 ms initializa-
tion period During this initialization period the DP8520A
21A 22A performs refreshes about every 15 s this makes
further VRAM warmup cycles unnecessary The chip can be
programmed as many times as the user wishes After the
first programming the 60 ms initialization period will not be
entered into unless the chip is reset Refreshes occur during
the 60 ms initialization period If ECAS0 was asserted during
programming the RFIP (RFRQ) pin will act as RFIP and will
be asserted throughout the initialization period otherwise
the pin will act like RFRQ and toggle every 13 s– 15 s in
conjunction with internal refresh requests If the user at-
tempts an access during the initialization period wait states
will be inserted into the access cycle until the initialization
period is complete and RAS precharge time has been met
The actual initialization time period is given by the following
formula
Pull-Up or Pull-Down Resistors on Each Address Input
T
e
4096 (Clock Divisor Select)
(Refresh Clock Fine Tune)
(DELCK Frequency)
FIGURE 46 Programming during System Reset
FIGURE 45 Mode Load Only Programming
37
9 1 MODE LOAD ONLY PROGRAMMING
MODE LOAD ML asserted enables an internal 23-bit pro-
grammable register To use this method the user asserts
ML enabling the internal programming register After ML is
asserted a valid programming selection is placed on the
address bus (and ECAS0) then ML is negated When ML is
negated the value on the address bus (and ECAS0) is
latched into the internal programming register and the
DP8520A 21A 22A is programmed as shown in Figure 45
After ML is negated the DP8520A 21A 22A will enter the
60 ms initialization period only if this is the first programming
after power up or reset
Using this method a set of transceivers on the address bus
can be put at TRI-STATE
combination of pull-up and pull-down resistors can be used
on the address inputs of the DP8520A 21A 22A to select
the programming values as shown in FIgure 46
9 2 CHIP SELECTED ACCESS PROGRAMMING
The chip can also be programmed by asserting ML and per-
forming a chip selected access ADS (or ALE) is disabled
internally until after programming To program the chip using
this method ML is asserted After ML is asserted CS is
asserted and a valid programming selection is placed on the
address bus When AREQ is asserted the chip is pro-
grammed with the programming selection on the address
bus After AREQ is negated ML can be negated as shown
in Figure 47
by the system reset signal A
TL F 9338 – 97
TL F 9338 – 96