DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 50

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

15 0 AC Timing Parameters DP8520A DP8521A DP8522A
Unless otherwise stated V
per bank including trace capacitance (see Note 2)
Two different loads are specified
C
C
Number
21
22
23
26
27
28
29a
29b
30
31
32
33
34a
34b
34c
34d
35
36
37
38
L
L
e
e
50 pF loads on all outputs except
150 pF loads on Q0–8 9 and 10 or
tPEDL
tPEDH
tSWCK
tPAQ
tPCINCQ
tSCINEN
tSARQCK1
tSARQCK2
tPAREQDH
tPCKCAS
tSCADEN
tWCINC
tPCKCL0
tPCKCL1
tPCKCL2
tPCKCL3
tCAH
tPCQR
tPCASDTH
tPCASDTL
Symbol
CC
e
5 0V
ECAS Asserted to DTACK
Asserted during a Burst Access
(Programmed as DTACK0)
ECAS Negated to DTACK
Negated during a Burst Access
WAITIN Asserted Setup to CLK
Row Column Address Valid to
Q0–8 9 10 Valid
COLINC Asserted to Q0–8 9 10
Incremented
COLINC Asserted Setup to ECAS
Asserted to Ensure tASC
AREQ Negated Setup to CLK
High with 1 Period of Precharge
AREQ Negated Setup to CLK High with
l
AREQ Negated to DTACK Negated
CLK High to CAS Asserted
when Delayed by WIN
Column Address Setup to ECAS
Asserted to Guarantee tASC
COLINC Pulse Width
CLK High to CAS Asserted following
Precharge (tRAH
CLK High to CAS Asserted following
Precharge (tRAH
CLK High to CAS Asserted following
Precharge (tRAH
CLK High to CAS Asserted following
Precharge (tRAH
Column Address Hold Time
(Interleave Mode Only)
CAS Asserted to Row Address
Valid (Interleave Mode Only)
CAS Asserted to DT OE
Asserted for a VRAM Read Access
CAS Negated to DT OE
Negated for a VRAM Read Access
1 Period of Precharge Programmed
g
10% 0 C
Common Parameter
Description
k
e
e
e
e
T
A k
15 ns tASC
25 ns tASC
25 ns tASC
25 ns tASC
70 C the output load capacitance is typical for 4 banks of 18 VRAMs
e
50
0 ns
e
0
C
C
C
e
e
e
e
H
H
H
0 ns)
0 ns)
0 ns)
10 ns)
e
e
e
50 pF loads on all outputs except
125 pF loads on RAS0– 3 and CAS0–3 and
380 pF loads on Q0– 8 9 and 10
Min
17
37
15
14
20
32
5
C
L
8520A 21A 22A-25
Max
38
14
14
(Continued)
38
26
30
27
25
72
82
82
92
90
Min
19
37
15
16
20
32
5
C
H
Max
38
38
35
39
27
32
79
89
89
99
90
24
24