DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 2

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

1 0 INTRODUCTION
2 0 SIGNAL DESCRIPTIONS
3 0 PORT A ACCESS MODES
4 0 REFRESH OPTIONS
5 0 PORT A WAIT STATE SUPPORT
6 0 DP8520A 21A 22A VIDEO RAM SUPPORT
2 1 Address R W and Programming Signals
2 2 VRAM Control Signals
2 3 Refresh Signals
2 4 Port A Access Signals
2 5 Port B Access Signals (DP8522A)
2 6 Common Dual Port Signals (DP8522A)
2 7 Power Signals and Capacitor Input
2 8 Clock Inputs
3 1 Access Mode 0
3 2 Access Mode 1
4 1 Refresh Control Modes
4 2 Refresh Cycle Types
4 3 Extending Refresh
4 4 Clearing the Refresh Address Counter
4 5 Clearing the Refresh Request Clock
5 1 WAIT Type Output
5 2 DTACK Type Output
5 3 Wait State Support for VRAM Transfer Cycles
5 4 Dynamically Increasing the Number of Wait States
5 5 Guaranteeing RAS Low Time and RAS Precharge
6 1 Support for VRAM Transfer Cycles
6 2 Support for VRAM Access Cycles through Port A
4 1 1 Automatic Internal Refresh
4 1 2 Externally Controlled Burst Refresh
4 1 3 Refresh Request Acknowledge
4 2 1 Conventional Refresh
4 2 2 Staggered Refresh
4 2 3 Error Scrubbing Refresh
Time
Table of Contents
2
7 0 ADDITIONAL ACCESS SUPPORT FEATURES
8 0 RAS AND CAS CONFIGURATION MODES
9 0 PROGRAMMING AND RESETTING
10 0 TEST MODE
11 0 VRAM CRITICAL TIMING OPTIONS
12 0 DUAL ACCESSING (DP8522A)
13 0 ABSOLUTE MAXIMUM RATINGS
14 0 DC ELECTRICAL CHARACTERISTICS
15 0 AC TIMING PARAMETERS
16 0 FUNCTIONAL DIFFERENCES BETWEEN THE
17 0 DP8520A 21A 22A USER HINTS
18 0 DESCRIPTION OF A DP8522A DP8500
7 1 Address Latches and Column Increment
7 2 Address Pipelining
7 3 Delay CAS During Write Accesses
8 1 Byte Writing
8 2 Memory Interleaving
8 3 Address Pipelining
8 4 Error Scrubbing
8 5 Page Burst Mode
9 1 Mode Load Only Programming
9 2 Chip Selected Access Programming
9 3 External Reset
9 4 Definition of Programming Bits
11 1 Programming Values of t
11 2 Calculation of t
12 1 Port B Access Mode
12 2 Port B Wait State Support
12 3 Common Port A and Port B Dual Port Functions
DP8520A 21A 22A AND THE DP8520 21 22
SYSTEM INTERFACE
12 3 1 GRANTB Output
12 3 2 LOCK Input
RAH
and t
RAH
ASC
and t
ASC