DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 42

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

9 0 Programming and Resetting
9 4 PROGRAMMING BIT DEFINITIONS (Continued)
Note 1 The configuration modes allow RASs and CASs to be grouped such that each RAS and CAS will drive one-fourth of the total VRAM array whether the array
is organized as 1 2 or 4 banks
Note 2 In order for a CAS output to go low during an access it must be both selected and enabled ECAS0–1 are used to enable the CAS outputs (ECAS0 enables
CAS0 1 ECAS1 enables CAS2 3) Selection is determined by the configuration mode and B1 B0
1
0 1
0 1
1 0
1 1
Symbol
R7
0
R6
0
1
R5 R4
0 0
0 1
1 0
1 1
R3 R2
0 0
1 0
1 1
R1 R0
0 0
WAIT or DTACK Select
WAIT type output is selected
DTACK (Data Transfer ACKnowledge) type output is selected
Add Wait States to the Current Access if WAITIN is Low
WAIT or DTACK will be delayed by one additional positive edge of CLK
WAIT or DTACK will be delayed by two additional positive edges of CLK
WAIT DTACK during Burst (See Section 5 1 2 or 5 2 2)
NO WAIT STATES If R7
If R7
1T If R7
WAIT will negate from the positive edge of CLK after the ECASs have been asserted
If R7
DTACK will assert from the positive edge of CLK after the ECASs have been asserted
asserted WAIT will negate on the negative level of CLK after the ECASs have been asserted
If R7
DTACK will assert from the negative level of CLK after the ECASs have been asserted
0T If R7
when the ECAS inputs are asserted
If R7
when the ECAS inputs are asserted
WAIT DTACK Delay Times (See Section 5 1 1 or 5 2 1)
NO WAIT STATES If R7
WAIT will negate when RAS is negated during delayed accesses
NO WAIT STATES If R7
1T If R7
RAS
NO WAIT STATES
WAIT will negate on the negative level of CLK after the access RAS during delayed accesses
RAS
1T If R7
1 T If R7
edge of CLK after the access RAS
RAS Low and RAS Precharge Time
RAS asserted during refresh
RAS precharge time
RAS will start from the first positive edge of CLK after GRANTB transitions (DP8522A)
RAS asserted during refresh
RAS precharge time
RAS will start from the second positive edge of CLK after GRANTB transitions (DP8522A)
RAS asserted during refresh
RAS precharge time
RAS will start from the first positive edge of CLK after GRANTB transitions (DP8522A)
RAS asserted during refresh
RAS precharge time
RAS will start from the second positive edge of CLK after GRANTB transitions (DP8522A)
T If R7
T If R7
T If R7
e
e
e
e
1 programming DTACK will remain asserted during burst portion of access
1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted
1 during programming DTACK will negate when the ECAS inputs are negated with AREQ asserted
1 during programming DTACK will negate when the ECAS inputs are negated DTACK will assert
e
e
e
e
e
e
e
e
0 during programming WAIT will assert when the ECAS inputs are negated with AREQ asserted
0 during programming WAIT will assert when the ECAS inputs are negated WAIT will negate
1 during programming DTACK will be asserted on the positive edge of CLK after the access
0 during programming WAIT will negate on the positive edge of CLK after the access RAS
0 during programming WAIT will assert when the ECAS inputs are negated with AREQ
0 during programming WAIT will negate on the negative level of CLK after the access RAS
1 during programming DTACK will be asserted on the negative level of CLK after the access
1 during programming DTACK will be asserted on the negative level of CLK after the positive
e
e
e
e
T If R7
1 positive edge of CLK
2 positive edges of CLK
2 positive edges of CLK
3 positive edges of CLK
e
e
e
0 during programming WAIT will remain negated during burst portion of access
0 during programming WAIT will remain high during non-delayed accesses
1 during programming DTACK will be asserted when RAS is asserted
e
e
e
e
e
2 positive edges of CLK
3 positive edges of CLK
2 positive edges of CLK
4 positive edges of CLK
0 during programming WAIT will remain high during non-delayed accesses
(Continued)
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Description