DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 21

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

5 0 Port A Wait State Support
5 4 DYNAMICALLY INCREASING THE NUMBER OF
WAIT STATES
The user can increase the number of positive edges of CLK
before DTACK is asserted or WAIT is negated With the
input WAITIN asserted the user can delay DTACK asserting
or WAIT negating either one or two more positive edges of
CLK The number of edges is programmed through address
bit R6 If the user is increasing the number of positive edges
in a delay that contains a negative level the positive edges
will be met before the negative level For example if the user
programmed DTACK of
grammed as 2T would increase the number of positive edg-
es resulting in DTACK of 2 T as shown in Figure 19 Simi-
larly WAITIN can increase the number of positive edges in
a page burst access WAITIN can be permanently asserted
in systems requiring an increased number of wait states
WAITIN can also be asserted and negated depending on
the type of access As an example a user could invert the
WRITE line from the CPU and connect the output to
WAITIN This could be used to perform write accesses with
1 wait state and read accesses with 2 wait states as shown
in Figure 20
FIGURE 19 WAITIN Example (DTACK is Sampled at the ‘‘T3’’ Falling Clock Edge)
T
asserting WAITIN
(Continued)
pro-
21
5 5 GUARANTEEING RAS LOW TIME AND RAS
PRECHARGE TIME
The DP8520A 21A 22A will guarantee RAS precharge time
between accesses between refreshes and between ac-
cess and refreshes The programming bits R0 and R1 are
used to program combinations of RAS precharge time and
RAS low time referenced by positive edges of CLK RAS
low time is programmed for refreshes only During an ac-
cess the system designer guarantees the time RAS is as-
serted through the DP8520A 21A 22A wait logic Since in-
serting wait states into an access increases the length of
the CPU signals which are used to create ADS or ALE and
AREQ the time that RAS is asserted can be guaranteed
Precharge time is also guaranteed by the DP8520A 21A
22A Each RAS output has a separate positive edge of CLK
counter AREQ is negated setup to a positive edge of CLK
to terminate the access That positive edge is 1T The next
positive edge is 2T RAS will not be asserted until the pro-
grammed number of positive edges of CLK have passed as
shown in Figure 21 Once the programmed precharge time
has been met RAS will be asserted from the positive edge
of CLK However since there is a precharge counter per
RAS an access using another RAS will not be delayed
Precharge time before a refresh is always referenced from
the access RAS negating before RAS0 for the refresh as-
serting After a refresh precharge time is referenced from
RAS3 negating for the refresh to the access RAS assert-
ing
TL F 9338 – 75