DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 4

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

1 0 Introduction
wait signal is active low The user can choose either at pro-
gramming These signals are used by the on-chip arbitor to
insert wait states to guarantee the arbitration between ac-
cesses and refreshes or precharge Both signals are inde-
pendent of the access mode chosen
DTACK will assert a programmed number of clock edges
from the event that starts the access RAS DTACK will be
negated when the access is terminated by AREQ being
negated DTACK can also be programmed to toggle with
the ECAS inputs during burst page mode accesses
WAIT is asserted during the start of the access (ALE and
CS or ADS and CS) and will negate a number of clock
edges from the event that starts the access RAS After
WAIT is negated it will stay negated until the next access
WAIT can also be programmed to toggle with ECAS inputs
during a burst page mode access
Both signals can be dynamically delayed further through the
WAITIN signal to the DP8520A 21A 22A
The DP8520A 21A 22A have address latches used to
latch the bank row and column address inputs Once the
address is latched a column increment feature can be used
to increment the column address The address latches can
also be programmed to be fall through
The RAS and CAS drivers can be configured to drive a one
two or four bank memory array up to 32 bits in width The
two ECAS signals can then be used to select one pair of
CAS drivers for byte writing with no external logic for sys-
tems with a word length of up to 16 bits
When configuring the DP8520A 21A 22A for more than
one bank memory interleaving can be used By tying the
low order address bits to the bank select lines B0 and B1
sequential back to back accesses will not be delayed since
the DP8520A 21A 22A have separate precharge counters
per bank The DP8520A 21A 22A are capable of perform-
ing address pipelining In address pipelining the DP8520A
21A 22A guarantee the column address hold time and
switch the internal multiplexor to place the row address on
the address bus At this time another memory access to
another bank can be initiated
(Continued)
4
The DP8522A has all the features previously mentioned
Unlike the DP8520A 21A the DP8522A has a second port
to allow a second CPU to access the memory array This
port Port B has two control signals to allow a CPU to ac-
cess the VRAM array These signals are access request for
Port B AREQB and Advanced Transfer ACKnowledge for
Port B ATACKB Two other signals are used by both Port A
and Port B for dual accessing purposes The signals are
lock LOCK and grant Port B GRANTB All arbitration for
the two ports and refresh is done on-chip by the DP8522A
through the insertion of wait states Since the DP8522A has
only one input address bus the address lines have to be
multiplexed externally The signal GRANTB can be used for
this purpose since it is asserted when Port B has access to
the VRAM array and negated when Port A has access to the
VRAM array Once a port has access to the array the other
port can be ‘‘locked out’’ by asserting the input LOCK
AREQB when asserted is used by Port B to request an
access ATACKB when asserted signifies that access RAS
has been asserted for the requested Port B access By us-
ing ATACKB the user can generate an appropriate WAIT or
DTACK like signal for the Port B CPU
The following explains the terminology used in this data
sheet The terms negated and asserted are used Asserted
refers to a ‘‘true’’ signal Thus ‘‘ECAS0 asserted’’ means
the ECAS0 input is at a logic 0 The term ‘‘COLINC assert-
ed’’ means the COLINC input is at a logic 1 The term negat-
ed refers to a ‘‘false’’ signal Thus ‘‘ECAS0 negated’’
means the ECAS0 input is at a logic 1 The term ‘‘COLINC
negated’’ means the input COLINC is at a logic 0 The table
shown below clarifies this terminology
Active High
Active High
Active Low
Active Low
Signal
Asserted
Asserted
Negated
Negated
Action
Logic Level
High
High
Low
Low