DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 41

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

9 0 Programming and Resetting
9 4 PROGRAMMING BIT DEFINITIONS (Continued)
C6 C5 C4
1 0 0
1 0 1
1 1 0
1 1 1
C3
0
1
C2 C1 C0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
R9
0
1
R8
0
1
Symbol
RAS and CAS Configuration Modes (Continued)
RAS pairs are selected by B1 CAS0– 3 are all selected For a particular CAS to be asserted its
corresponding ECAS input must be asserted
B1
B1
B0 is not used during an access
No error scrubbing
RAS and CAS pairs are selected by B1 For a particular CAS to be asserted its corresponding ECAS input
must be asserted
B1
B1
B0 is not used during an access
No error scrubbing
RAS singles are selected by B0–1 CAS0– 3 are all selected For a particular CAS to be asserted its
corresponding ECAS input must be asserted
B1
B1
B1
B1
No error scrubbing
RAS and CAS singles are selected by B0 1 For a particular CAS to be asserted its corresponding ECAS
input must be asserted
B1
B1
B1
B1
No error scrubbing
Refresh Clock Fine Tune Divisor
Divide delay line refresh clock further by 30 (If DELCLK Refresh Clock Clock Divisor
refresh period)
Divide delay line refresh clock further by 26 (If DELCLK Refresh Clock Clock Divisor
refresh period)
Delay Line Refresh Clock Divisor Select
Divide DELCLK by 10 to get as close to 2 MHz as possible
Divide DELCLK by 9 to get as close to 2 MHz as possible
Divide DELCLK by 8 to get as close to 2 MHz as possible
Divide DELCLK by 7 to get as close to 2 MHz as possible
Divide DELCLK by 6 to get as close to 2 MHz as possible
Divide DELCLK by 5 to get as close to 2 MHz as possible
Divide DELCLK by 4 to get as close to 2 MHz as possible
Divide DELCLK by 3 to get as close to 2 MHz as possible
Refresh Mode Select
RAS0–3 will all assert and negate at the same time during a refresh
Staggered Refresh RAS outputs during refresh are separated by one positive clock edge Depending on the
configuration mode chosen either one or two RASs will be asserted
Address Pipelining Select
Address pipelining is selected The VRAM controller will switch the VRAM column address back to the row
address after guaranteeing the column address hold time
Non-address pipelining is selected The VRAM controller will hold the column address on the VRAM address
bus until the access RASs are negated
e
e
e
e
e
e
e
e
e
e
e
e
0 during an access selects RAS0– 1 and CAS0 –3
1 during an access selects RAS2– 3 and CAS0 –3
0 during an access selects RAS0– 1 and CAS0 –1
1 during an access selects RAS2– 3 and CAS2 –3
0 B0
0 B0
1 B0
1 B0
0 B0
0 B0
1 B0
1 B0
e
e
e
e
e
e
e
e
0 during an access selects RAS0 and CAS0– 3
1 during an access selects RAS1 and CAS0– 3
0 during an access selects RAS2 and CAS0– 3
1 during an access selects RAS3 and CAS0– 3
0 during an access selects RAS0 and CAS0
1 during an access selects RAS1 and CAS1
0 during an access selects RAS2 and CAS2
1 during an access selects RAS3 and CAS3
(Continued)
41
Description
e
e
2 MHz
2 MHz
e
e
15 s
13 s