DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 54

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

15 0 AC Timing Parameters DP8520A DP8521A DP8522A
Unless otherwise stated V
per bank including trace capacitance (see Note 2)
Two different loads are specified
C
C
Number
300
301a
301b
302
303
304
305
306
307
308a
308b
308c
308d
309
310
311
312
313
314
315
L
L
e
e
50 pF loads on all outputs except
150 pF loads on Q0–8 9 and 10 or
tSCSCK
tSALECKNL
tSALECKL
tWALE
tSBADDCK
tSADDCK
tHASRCB
tSRCBAS
tPCKRL
tPCKCL0
tPCKCL1
tPCKCL2
tPCKCL3
tHCKALE
tSWINCK
tPCSWL
tPCSWH
tPCLKDL1
tPALEWL
Symbol
CC
e
5 0V
CS Asserted to CLK High
ALE Asserted Setup to CLK High
Not Using On-Chip Latches or
if Using On-Chip Latches and
B0 B1 Are Constant Only 1 Bank
ALE Asserted Setup to CLK High
if Using On-Chip Latches if B0 B1
Can Change More Than One Bank
ALE Pulse Width
Bank Address Valid Setup to CLK High
Row Column Valid Setup to
CLK High to Guarantee
tASR
Row Column Bank Address
Held from ALE Negated
(Using On-Chip Latches)
Row Column Bank Address
Setup to ALE Negated
(Using On-Chip Latches)
CLK High to RAS Asserted
CLK High to CAS Asserted
(tRAH
CLK High to CAS Asserted
(tRAH
CLK High to CAS Asserted
(tRAH
CLK High to CAS Asserted
(tRAH
ALE Negated Hold from CLK High
WIN Asserted Setup to CLK High
to Guarantee CAS is Delayed
CS Asserted to WAIT Asserted
CS Negated to WAIT Negated
CLK High to DTACK Asserted
(Programmed as DTACK0)
ALE Asserted to WAIT Asserted
(CS is Already Asserted)
AREQ Negated to CLK High That Starts
Access RAS to Guarantee tASR
(Non-Interleaved Mode Only)
g
10% 0 C
e
e
e
e
e
Parameter Description
0 ns
15 ns tASC
15 ns tASC
25 ns tASC
25 ns tASC
Mode 0 Access
k
T
A k
e
e
e
e
70 C the output load capacitance is typical for 4 banks of 18 VRAMs
0 ns)
10 ns)
0 ns)
10 ns)
54
C
C
C
e
H
H
H
0 ns
e
e
e
50 pF loads on all outputs except
125 pF loads on RAS0– 3 and CAS0–3 and
380 pF loads on Q0– 8 9 and 10
b
Min
13
15
29
13
18
11
34
8
2
0
16
C
L
8520A 21A 22A-25
Max
22
72
82
82
92
22
25
32
29
(Continued)
b
Min
13
15
29
13
18
16
39
8
2
0
16
C
H
Max
26
79
89
89
99
22
25
32
29