DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 40

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

9 0 Programming and Resetting
9 4 PROGRAMMING BIT DEFINITIONS
ECAS0
0
1
B1
0
1
B0
0
1
C9
0
1
C8
0
1
C7
0
1
C6 C5 C4
0 0 0
0 0 1
0 1 0
0 1 1
Symbol
Extend CAS Refresh Request Select
The CASn outputs will be negated with the RASn outputs when AREQ (or AREQB DP8522A only) is
negated The RFIP pin will function as refresh in progress During a video shift register load operation the
DT OE output will be negated by either the 4th rising clock edge after the input VSRL asserts or by the
VSRL input negating whichever occurs first when this mode is programmed
The CASn outputs will be negated during an access (Port A (or Port B DP8522A only)) when their
corresponding ECASn inputs are negated This feature allows the CAS outputs to be extended beyond the
RAS outputs negating Scrubbing refreshes are NOT affected During scrubbing refreshes the CAS outputs
will negate along with the RAS outputs regardless of the state of the ECAS inputs
The RFIP output will function as ReFresh ReQuest (RFRQ) when this mode is programmed The DT OE
output will be negated by the input VSRL negating when this mode is programmed
Access Mode Select
ACCESS MODE 0 ALE pulsing high sets an internal latch On the next positive edge of CLK the access
(RAS) will start AREQ will terminate the access
ACCESS MODE 1 ADS asserted starts the access (RAS) immediately AREQ will terminate the access
Address Latch Mode
ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GRANT latch the input
row column and bank address
The row column and bank latches are fall through
Delay CAS during WRITE Accesses
CAS is treated the same for both READ and WRITE accesses
During WRITE accesses CAS will be asserted by the event that occurs last CAS asserted by the internal
delay line or CAS asserted on the positive edge of CLK after RAS is asserted
Row Address Hold Time
Row Address Hold Time
Row Address Hold Time
Column Address Setup Time
Column Address Setup Time
Column Address Setup Time
RAS and CAS Configuration Modes Error Scrubbing during Refresh
RAS0–3 and CAS0–3 are all selected during an access For a particular CAS to be asserted its
corresponding ECAS input must be asserted B0 and B1 are not used during an access Error scrubbing
during refresh
RAS and CAS pairs are selected during an access by B1 For a particular CAS to be asserted its
corresponding ECAS input must be asserted
B1
B1
B0 is not used during an Access
Error scrubbing during refresh
RAS and CAS singles are selected during an access by B0 – 1 For a particular CAS to be asserted its
corresponding ECAS input must be asserted
B1
B1
B1
B1
Error scrubbing during refresh
RAS0–3 and CAS0–3 are all selected during an access For a particular CAS to be asserted its
corresponding ECAS input must be asserted
B1 B0 are not used during an access
No error scrubbing (RAS only refreshing)
e
e
e
e
e
e
0 during an access selects RAS0–1 and CAS0–1
1 during an access selects RAS2–3 and CAS2–3
0 B0
0 B0
1 B0
1 B0
e
e
e
e
0 during an access selects RAS0 and CAS0
1 during an access selects RAS1 and CAS1
0 during an access selects RAS2 and CAS2
1 during an access selects RAS3 and CAS3
e
e
25 ns minimum
15 ns minimum
e
e
10 ns minimum
0 ns minimum
(Continued)
40
Description