DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 66

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

18 0 Description of a DP8522A DP8500 System Interface
The main idea of the block diagram in Figure 73 is to cause
the video DRAM shift register load operation to happen cor-
rectly Once the DP8500 (RGP) issues the Display Refresh
REQuest signal (DRREQ) the system knows that the video
shift register load operation should occur at a certain de-
fined time later In the block diagram this time is controlled
by the counter device This counter determines when VSRL
transitions high thereby causing the video shift register load
operation
In the upper part of the block diagram is the ‘‘REFRESH’’
output that is used as the ‘‘VSRL’’ input of the DP8522A
and is also used to create ‘‘REFRESH NOT DONE’’ To
creat the ‘‘REFRESH’’ output a NAND latch is used This
latch is set when a screen refresh is in progress shown by
the RGP outputs ALE B0 and B1 all being high If the
status of the RGP is anything other than screen refresh the
latch is reset The latch is also reset during a screen refresh
when the load shift register counter times out This counter
determines when the ‘‘VSRL’’ input of the DP8522A tran-
sitions high causing the video DRAMs to load a row of data
into their shift registers
The ‘‘REFRESH’’ signal along with the load shift register
counter output ‘‘NOT DONE’’ are used to create the
‘‘REFRESH NOT DONE’’ signal This output is used for two
purposes One of which is to hold the ‘‘WAIT’’ output low
thereby inserting WAIT states into the RGP video shift regis-
ter load access The other purpose is to hold ‘‘DT OE’’ low
until ‘‘VSRL’’ transitions high
FIGURE 70 DP8422A DP8500 (RGP) Interface Block Diagram
66
Important setup timing parameters which must be met for a
DP8500(RGP)– DP8522A system (assuming RGP is running
at 20 MHz (T
1 Address Setup to ADS Asserted
2 ADS Setup to Clock Rising Edge
3 WAIT Negated Setup to Clock
Note 1 ‘‘$’’ symbol refers to a DP8520A 21A 22A timing parameter
Note 2 ‘‘ ’’ symbol refers to a DP8500 timing parameter
Note 3 ALE asserted by the RGP (DP8500) should use the system PAL to
assert WAIT in order to guarantee proper setup time DTACK low should
then be used to negate the WAIT signal through PAL equations
Load
AREQ
(Using Light Load Timing Specs the DP8520A 21A 22A
Needs)
9 ns Setup for Row Address to ADS Asserted
11 ns Setup for Bank Address to ADS Asserted
e
e
e
e
e
e
e
e
e
(DP8520A 21A 22A Needs 7 ns)
(The DP8500 Needs 5 ns Setup Time)
1 T
50 ns
11 ns
1 T
50 ns
14 ns
1 T
50 ns
12 ns
CP
b
CP
CP
b
t
b
b
b
b
b
PF373
CP
38 ns
26 ns
28 ns
$18
t
e
t
ALV
ALEV
a
50 ns))
b
b
b
a
a
Max PAL Delay
Min PAL Delay to Produce ADS
b
Derating the DP8500 Spec for Light
10 ns
10 ns
5 ns
Max PAL Delay
(Continued)
b
8 ns
a
2 ns
TL F 9338 – C4