DP8522AV-25 National Semiconductor, DP8522AV-25 Datasheet - Page 24

• Manufacturer Part Number: DP8522AV-25
• Description: IC CTRLR 4M VRAM 25MHZ 68PLCC
• Manufacturer: National Semiconductor

Specifications of DP8522AV-25

• Controller Type: Video RAM Controller, Drivers
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Voltage - Supply: -
• Interface: -
• Other names: *DP8522AV-25

6 0 DP8520A 21A 22A Video RAM Support
6 1 SUPPORT FOR VRAM TRANSFER CYCLES
(TO THE SERIAL PORT OF THE VRAM)
The DP8520A 21A 22A supports VRAM transfer cycles
with the serial port in the active or standby mode Active or
standby refers to whether data is or is not currently being
shifted in or out of the VRAM serial port (i e whether the
shift clock (SCLK) is currently active) The DP8520A
21A 22A support for data transfer cycles with the serial port
in the active mode includes the ability to support transfer
cycles with the serial port in the standby mode Hereafter
the term VRAM transfer cycle means VRAM transfer cycle
with the serial port in the active mode
In order to support VRAM transfer cycles the DP8520A
21A 22A must be able to guarantee timing with respect to
its input CLK (which must be synchronous to VRAM shift
clock) RAS CAS and DT OE Figure 23 shows the timing
of
DP8520A 21A 22A is being used with the National Semi-
conductor DP8500 Raster Graphics Processor (RGP) If the
DP8520A 21A 22A is being used in a graphics frame buffer
application it has the ability to support a VRAM transfer
cycle during active video time (ex mid scan line) This is one
of the very attractive features supported by the National
Semiconductor Advanced Graphics chip set Most of the
commercial graphics controller chip sets available will only
support VRAM transfer cycles during blanking periods
(while the VRAM is in standby mode)
The DP8520A 21A 22A supports VRAM transfer cycles
during active video time by being able to guarantee an exact
instant during which the transfer of VRAM data to the VRAM
shift register will occur This exact instant can be guaran-
teed through the AVSRLRQ and VSRL inputs
The input AVSRLRQ disables any further internally or exter-
nally requested refreshes or Port B access requests from
being executed The AVSRLRQ input does this by making
the VRAM controller arbitration logic think that a Port A ac-
cess is in progress from the point where the AVSRLRQ in-
put asserts until the VRAM shift register load operation is
a
graphics
memory
system
where
the
24
completed Figure 23 shows the case of an externally re-
quested refresh being disabled because of a previous
AVSRLRQ until the VRAM shift register load has been
completed
The VSRL input causes the DT OE output to assert immedi-
ately regardless of what else may be happening in the
DP8520A 21A 22A Therefore it is the system designer’s
responsibility to guarantee that all pending accesses have
been completed by the time the VSRL input asserts The
system designer can guarantee this by issuing AVSRLRQ
far enough in advance to guarantee that all pending access-
es have been completed by the time VSRL asserts
The AVSRLRQ input does not override the LOCK input (see
Section 12 0) for dual port systems and as a result the
designer must also guarantee that Port A can be accessed
by assuring that GRANTB and LOCK are both not asserted
when AVSRLRQ is asserted
Generally the VSRL is the status of the upcoming access
cycle (of the graphics processor) Therefore this input pre-
cedes the inputs ADS and AREQ that execute the VRAM
shift register load transfer cycle This sequence of events
guarantees the correct relationship of DT OE RAS and
CAS (DT preceding RAS and CAS when asserting and neg-
ating) The wait logic is also intimately connected to the
graphics functions on the DP8520A 21A 22A The DT OE
(and WAIT DTACK) relationship to VSRL during a VRAM
transfer cycle depends upon how the DP8520A 21A 22A
was programmed with respect to the ECAS0 input If ECAS0
was negated during programming the DT OE output will
follow the VSRL input If ECAS0 was asserted during pro-
gramming the DT OE output will follow VSRL asserting
DT OE will then negate either when VSRL negates or from
the fourth rising clock edge after VSRL asserted whichever
event takes place first This allows DT to negate before
RAS and CAS negate thus guaranteeing the correct timing
relationship during the transfer cycle (see Figure 23 ) The
WE input of the VRAM determines whether the access is a
read or write transfer cycle (see Figures 24 and 25 respec-
tively)
(Continued)