CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 24

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

Manchester Encoder and Decoder. Selection is
made via:
3.1.3.7
The carrier detect circuit informs the MAC that val-
id receive data is present by asserting the Carrier
Sense signal (CRS) as soon it detects a valid bit pat-
tern (1010b or 0101b for 10BASE-T). During nor-
mal packet reception, CRS remains asserted while
the frame is being received, and is de-asserted
within 2.3 bit times after the last low-to-high tran-
sition of the End-of-Frame (EOF) sequence. When-
ever the receiver is idle (no receive activity), CRS
is de-asserted.
3.1.4
This mode is selected when pin 10BT_SERis as-
serted during power-up or reset, and operates simi-
lar to the 10BASE_T MII mode except that data is
transferred serially on pins RXD0 and TXD0 using
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
-
-
-
setting bit 14 in the Basic Mode Control
Register (address 00h) or
setting bits 8 and 11 in the Loopback, By-
pass, and Receiver Error Mask Register
(address 18h) or
asserting the LPBK pin.
10BASE-T Serial Application
Carrier Detection
a 10 MHz RX_CLK and TX_CLK. Receive data is
framed by CRS rather than RX_DV.
3.2
The CS8952 supports auto-negotiation, which is
the mechanism that allows the two devices on ei-
ther end of an Ethernet link segment to share infor-
mation and automatically configure both devices
for maximum performance. When configured for
auto-negotiation, the CS8952 will detect and auto-
matically operate full-duplex at 100 Mb/s if the de-
vice on the other end of the link segment also
supports full-duplex, 100 Mb/s operation, and
auto-negotiation. The CS8952 auto-negotiation ca-
pability is fully compliant with the relevant por-
tions of section 28 of the IEEE 802.3u standard.
The CS8952 can auto-negotiate both operating
speed (10 versus 100 Mb/s), duplex mode (half du-
plex versus full duplex), and flow control (pause
frames), or alternatively can be set not to negotiate.
At power-up and reset times, the auto-negotiation
mode is selected via the auto-negotiation input pins
(AN[1:0]). This selection can later be changed us-
ing the Auto-Negotiation Advertisement Register
(address 04h).
Pins AN[1:0] are three level inputs, and have the
function shown in Table 5.
Auto-Negotiation
CS8952
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