CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 61

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

6.20
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
15:8
7
6
5
4
3
2
1
Compatibility
BIT
National
Mode
15
7
Reserved
National Compati-
bility Mode
LED3 Blink Enable Read/Write 0
Enable LT/10
SQE Enable
Reserved
Low Rx Squelch
Polarity Disable
10BASE-T Configuration Register - Address 1Ch
NAME
LED3 Blink
Enable
14
6
Read Only 0000 0000
Read/Write 1
Read/Write 1
Read/Write Reset to the logic
Read Only 1
Read/Write 0
Read/Write 0
Enable LT/10
TYPE
13
5
inverse of the
value on the
REPEATER pin.
SQE Enable
RESET
12
4
Reserved
Reserved
When set, registers and bits that are not compatible
with the National DP83840 are disabled and writes to
these registers are ignored.
When set, LED3 will blink during auto-negotiation
and will indicate Link Good status upon completion of
auto-negotiation. When clear, LED3 indicates Link
Good status only.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
When set, this bit enables the transmission of link
pulses.
When clear, link pulses are disabled and a good link
condition is forced. If link pulses are disabled during
100 Mb/s operation with auto-negotiation enabled,
the CS8952 will go into 10 Mb/s mode. If operating in
100 Mb/s mode with no auto-negotiation, then clear-
ing this bit has no effect.
When set, and if the CS8952 is in half-duplex mode,
this bit enables the 10BASE-T SQE function. When
the part is in repeater mode, this bit is cleared and
may not be set.
This bit should be read as a don’t care and, when
written, should be written to 1.
When clear, the 10BASE-T receiver squelch thresh-
olds are set to levels defined by the ISO/IEC 8802-3
specification. When set, the thresholds are reduced
by approximately 6 dB. This is useful for operating
with “quiet” cables that are longer than 100 meters.
The 10BASE-T receiver automatically determines
the polarity of the received signal at the RXD+/RXD-
input. When this bit is clear, the polarity is corrected,
if necessary. When set, no effort is made to correct
the polarity. Polarity correction will only be performed
during 10BASE-T packet reception.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit (bit
7) is set.
11
3
Squelch
Low Rx
10
2
DESCRIPTION
Polarity
Disable
9
1
Jabber Enable
CS8952
8
0
61