CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 31

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

6.1
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
15
14
13
12
11
10
Collision Test
BIT
Software
Reset
15
7
Software Reset
Loopback
Speed Selection
Auto-Neg Enable
Power Down
Isolate
Basic Mode Control Register - Address 00h
NAME
Loopback
14
6
Read/Set
Read/Write 0
Read/Write If auto-negotiation
Read/Write If auto-negotiation
Read/Write 0
Read/Write If PHYAD =
Selection
TYPE
Speed
13
5
0
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0
00000, reset to 1;
otherwise reset to
the value on the
ISODEF pin
Auto-Neg
Enable
RESET
12
4
Power Down
Reserved
Setting this bit performs a chip-wide reset. All status
and control registers are set to their default states,
and the analog circuitry is re-calibrated. This bit is an
Act-Once bit which is cleared once the reset and re-
calibration have completed.
This bit will also be set automatically while the analog
circuitry is reset and re-calibrated during mode
changes.
When set, the CS8952 is placed in a loop back
mode. Any data sent on the transmit data path is
returned on the receive data path. Loopback mode is
entered regardless of whether 10 Mb/s or 100 Mb/s
operation has been configured.
This bit will be set upon the assertion of the LPBK
pin, and will be automatically cleared upon its deas-
sertion.
When bit 12 is clear, setting this bit configures the
CS8952 for 100 Mb/s operation. Clearing this bit sets
the configuration at 10 Mb/s. When bit 12 is set, this
bit is ignored.
Setting this bit enables the auto-negotiation process.
When this bit is set, bits 13 and 8 have no affect on
the link configuration. The link configuration is deter-
mined by the auto-negotiation process. Clearing this
bit disables auto-negotiation.
When this bit is set, the CS8952 enters a low power
consumption state. Clearing this bit allows normal
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
Setting this bit causes the MII data path to be electri-
cally isolated by tri-stating all data outputs (i.e.
TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL,
and CRS). In addition the CS8952 will not respond to
the TXD[3:0], TX_EN, and TX_ER inputs. It will, how-
ever, respond to MDIO and MDC. Clearing this bit
allows normal operation.
11
3
Isolate
10
2
DESCRIPTION
Auto-Neg
Restart
9
1
Duplex Mode
CS8952
8
0
31