CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 43

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
5
4
3
2
1
0
BIT
Auto-Neg Complete Read/Write 0
Parallel Detection
Fault
Parallel Fail
Remote Fault
Page Received
Reserved
NAME
Read/Write 0
Read/Write 0
Read/Write 0
Read/Write 0
Read Only 0
TYPE
RESET
When set, an interrupt will be generated once auto-
negotiation has completed successfully.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if auto-nego-
tiation determines that unstable legacy link signaling
was received.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when paral-
lel detection has occurred for a technology that is not
currently advertised by the local device.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated if a remote
fault condition is detected either by auto-negotiation
or by the Far-End Fault Detect state machine.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt is generated each time a page
is received during auto-negotiation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DESCRIPTION
CS8952
43