CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 71

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

TX_EN - Transmit Enable. Input, Pin 43.
TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38.
TXD[3:0] - Transmit Data. Input, Pins 47, 46, 45, and 44.
Control and Status Pins
10BT_SER - 10 Mb/s Serial Mode Select. Input, Pin 23.
AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
When the TCM pin is high on power-up or reset, the CLK25 pin may be used as a source for the
TX_CLK pin. When the TCM pin is floating on power-up or reset, TX_CLK must be supplied externally.
TX_CLK should have the following nominal frequency:
Asserted high to indicate valid data nibbles are present on TXD[3:0]. When BPALIGN is selected,
TX_EN must be pulled up to VDD_MII.
When high, TX_ER indicates to the CS8952 that a transmit error has occurred. If TX_ER is asserted
simultaneously with TX_EN in 100 Mb/s mode, the CS8952 will ignore the data on the TXD[3:0] pins
and transmit one or more 100 Mb/s HALT symbols in its place. In 10 Mb/s mode, TX_ER has no effect
on the transmitted data.
If BP4B5B or BPALIGN are set, TX_ER/TXD4 is used to transmit the most-significant bit of the five-bit
code group.
Transmit data input pins. For MII modes, nibble-wide data (synchronous to TX_CLK) must be presented
on pins TXD[3:0] when TX_EN is asserted high. TXD0 is the least significant bit. In 10 Mb/s serial
mode, pin TXD0 is used as the serial input pin, and TXD[3:1] are ignored.
When either BP4B5B or BPALIGN is selected, pin TXD4 contains the most significant bit of the five-bit
code-group.
When asserted high during power-up or reset and 10 Mb/s operation is selected, serial data will be
transferred on pins RXD0 and TXD0. When low during power-up or reset and 10 Mb/s operation is
selected, data is transferred a nibble at a time on RXD[3:0] and TXD[3:0]. This pin is ignored during
100 Mb/s operation.
10 Mb/s serial mode may also be entered under software control through bit 9 of the 10BASE-T Status
Register (address 1Bh).
At power-up or at reset, the value on this pin is latched into bit 9 of the 10BASE-T Status Register
(address 1Bh). This pin includes a weak internal pull-down (> 20 kΩ), or the value may be set by an
external 4.7 kΩ pull-up or pull-down resistor.
These three-level input pins are sampled during power-up or reset. They control the forced or
advertised auto-negotiation operating modes. If one of these pins is left unconnected, internal logic pulls
its signal to a mid-range value, 'M'.
AN1 pin
0
100 Mb/s
10 Mb/s
10 Mb/s
Speed
AN0 pin
M
10 Mb/s
10BT_SER pin
Speed
low (parallel)
high (serial)
n/a
Forced/Auto
Forced
Nominal frequency
2.5 MHz
25 MHz
10 MHz
Full/Half Duplex
Half
CS8952
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