CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 52

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

6.16
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
15
14
13
12
11
10
CLK25 Disable Enable LT/100
NRZI Enable
BIT
15
7
NRZI Enable
Time-Out Select
Time-Out Disable
Repeater Mode
LED5 Mode
Unlock Regs
PCS Sub-Layer Configuration Register - Address 17h
NAME
Time-Out
Select
14
6
Read/Write 1
Read/Write 0
Read/Write 0
Read/Write Reset to the value
Read/Write 0
Read/Write 0
CIM Disable
Time-Out
TYPE
Disable
13
5
on the
REPEATER pin.
Tx Disable
Repeater
RESET
Mode
12
4
LED5 Mode
Rx Disable
When this bit is set, the NRZI encoder and decoder
are enabled. When this bit is clear, NRZI encoding
and decoding are disabled.
When this bit is set, the time-out counter in the
receive descrambler is set to time-out after 2 ms
without IDLES. When clear the counter is set to time-
out after 722 µs without IDLES.
When this bit is set, the time-out counter in the
receive descrambler is disabled. When this bit is
clear, the time-out counter is enabled.
This bit defines the mode of the Carrier Sense (CRS)
signal. When this bit is set, CRS is asserted due to
receive activity only. When this bit is clear, CRS is
asserted due to either transmit or receive activity.
This bit defines the mode of Pin LED5. When this bit
is set, pin LED5 indicates the synchronization status
of the 100BASE-TX descrambler. When this bit is
clear, LED5 indicates a collision.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, this bit unlocks certain read only control
registers for factory testing. Leave clear for proper
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
11
3
Unlock Regs
LED1 Mode
10
2
DESCRIPTION
MR Preamble
LED4 Mode
Enable
9
1
CS8952
Digital Reset
Fast Test
8
0
52