CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 28

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

specification, while the remaining registers provide
enhanced monitoring and control capabilities.
As many as 31 devices may share a single Manage-
ment Interface. A unique five-bit PHY address is
associated with each device, with all devices re-
sponding to PHY address 00000. The CS8952 de-
termines its PHY address at power-up or reset
through the PHYAD[4:0] pins.
4.5
Frames transmitted through the MII Management
Interface have the following format (Table 6):
The Start of Frame is indicated by a 01 bit pattern.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
TXD[3:0]
TXD[3:0]
TX_CLK
TX_CLK
Preamble
TX_EN
TX_ER
TX_EN
TX_ER
(32 bits)
MII Management Frame Structure
Start of
(2 bits)
Frame
Table 6. Format for Frame Transmitted through the MII Management Interface
Preamble/SFD
Preamble/SFD
Opcode
(2 bits)
Figure 4. Transmission without errors
Figure 5. Transmission with errors
Address
(5 bits)
PHY
When the management interface is idle, the MDIO
signal will be tri-stated, and the MAC is required to
keep MDIO pulled to a logic ONE.
At the beginning of each transaction, the MAC will
typically send a sequence of 32 contiguous logic
ONE bits on MDIO with 32 corresponding clock
cycles on MDC to provide the CS8952 with a pat-
tern that it can use to establish synchronization.
Optionally, the CS8952 may be configured to oper-
ate without the preamble through bit 9 of the PCS
Sub-Layer Configuration Register (address 17h).
Register
Address
(5 bits)
DATA
DATA
Turnaround
(2 bits)
HALT
(16 bits)
Data
CS8952
Idle
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