CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 41

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

6.9
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
15
14
13
12
BIT
Complete
CIM Link
Unstable
Reset
15
7
CIM Link Unstable
Link Status Change Read Write 1
Descrambler Lock
Change
Premature End
Error
Interrupt Mask Register - Address 10h
NAME
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as
an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ pin to be asserted. When
clear, the event will not affect the MII_IRQ pin, but the status will still be reported via the Interrupt Sta-
tus Register (address 11h).
Link Status
Change
Jabber
Detect
14
6
Read/Write 0
Read/Write 0
Read/Write 0
Lock Change
Descrambler
Auto-Neg
Complete
TYPE
13
5
Premature End
Detection Fault
Parallel
RESET
Error
12
4
Rollover
Parallel
When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the CS8952 detects a change in the link status.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the ESD sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
DCR
Fail
11
3
Rollover
Remote
FCCR
Fault
10
2
DESCRIPTION
Received
Rollover
RECR
Page
9
1
CS8952
Loopback
Reserved
Remote
Fault
8
0
41