CS8952-IQZ Cirrus Logic Inc, CS8952-IQZ Datasheet - Page 27

• Manufacturer Part Number: CS8952-IQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-IQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1208

onto RXD[3:0] synchronously with respect to
RX_CLK.
Receive errors are indicated during frame reception
by the assertion of RX_ER. It indicates that an error
was detected somewhere in the frame currently be-
ing transferred across the MII. RX_ER will transi-
tion synchronously with respect to the RX_CLK,
and will be held high for one cycle for each error re-
ceived. It is up to the MAC to ensure that a CRC er-
ror is detected in that frame by the Logical Link
Control. Figure 2 illustrates reception without er-
rors, and Figure 3 illustrates reception with errors.
4.3
TX_EN is used by the MAC to signal to the
CS8952 that valid nibbles of data are being present-
ed across the MII via TXD[3:0]. TX_EN must be
asserted synchronously with the first nibble of pre-
amble, and must remain asserted as long as valid
data is being presented to the MII.
TX_EN must be de-asserted within one TX_CLK
cycle after the last nibble of data (CRC) has been
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
RXD[3:0]
RXD[3:0]
RX_CLK
RX_CLK
RX_DV
RX_ER
RX_DV
RX_ER
MII Transmit Data
Preamble/SFD
Preamble/SFD
Figure 2. Reception without errors
Figure 3. Reception with errors
presented to the CS8952. When TX_EN is not as-
serted, data on TXD[3:0] is ignored.
Transmit errors should be signaled by the MAC by
asserting TX_ER for one or more TX_CLK cycles.
TX_ER must be synchronous with TX_CLK. This
will cause the CS8952 to replace the nibble with a
HALT symbol in the frame being transmitted. This
invalid data will be detected by the receiving PHY
and flagged as a bad frame. Figure 4 illustrates
transmission without errors, and Figure 5 illustrates
transmission with errors.
4.4
The CS8952 provides an enhanced IEEE 802.3 MII
Management Interface. The interface consists of
three signals: a bi-directional serial data line
(MDIO), a data clock (MDC), and an optional in-
terrupt signal (MII_IRQ). The Management Inter-
face can be used to access status and control
registers internal to the CS8952. The CS8952 im-
plements an extended set of 16-bit MII registers.
Eight of the registers are defined by the IEEE 802.3
DATA
DATA
MII Management Interface
XX
DATA
CS8952
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