PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 18

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Figure 4
DFE-T chip sets:
One AFE PLL generates the synchronized 15.36 MHz clock and provides the master
clock at pin CL15 for the other 3 devices. The internal PLL of the first AFE synchronizes
the 15.36 MHz master clock onto a PTT reference clock of either 8 kHz or 2048 kHz.
Infineon recommends to feed the FSC clock input of the DFE-T V2.2 and the PLL
reference clock input (pin CLOCK) of the AFE from the same clock source.
The PLL of the second AFE is deactivated. The 15.36 MHz master clock is applied at pin
CL15. CL15 is configured as input if XIN is clamped either to VDD or to VSS. Pin XOUT
has to be left open and CLOCK shall be tied to GND.
Figure 4
The DFE-T devices are supplied by the first AFE at pin CL15 with the synchronized
15.36 MHz clock. The IOM
programmed by the two slot pins. Starting from channel no. 0/4/8/12 always four
subsequent channels are occupied.
Data Sheet
4x U
4x U
shows how a 8 channel line card application is realized by use of two AFE/
Connecting Two AFE/DFE-T Chip Sets
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
Hybrid
®
VDD/
VSS
XIN
XIN
-2 channels the DFE-T devices are assigned to can be
15.36 MHz
AFE V2.1
AFE V2.1
PEF 24902
PEF 24902
XOUT
XOUT
N.C.
8/ 2048 kHz PTT
Reference Cock
CLOCK
CLOCK
VSS
CL15
CL15
19
15.36MHz
PDM0..3
PDM0..3
SDR
SDX
SDX
SDR
15.36MHz
CL15
CL15
DFE-T V2.2
DFE-T V2.2
PEF 24901
PEF 24901
clkchain1
1-4MBit/s
IOM
FSC
DCL
DIN
DOUT
Introduction
PEF 24901
2002-09-30
®
-2
DFE-T