PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 3

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Data Sheet
Revision History:
Previous Version:
Page
Chapter 1
Chapter 1.1
Figure
Figure
Table 1
Chapter 1.3
Page 19
Figure 4
Table
Table 2
Table 1
Table 1
Table 1
Chapter 2.3
Table 3
Chapter 3.1
Chapter 3.2.2
Chapter 3.2.3
Chapter 3.2.3
Chapter 3.3
Data Sheet
1,
2,
6,
Subjects (major changes since last revision)
update related documents
conforms to ITU-T G.961 (not ITU-T I.430)
removed transparent channel
Removed: Sophisticated power management for restricted power
mode
Removed: Monitor Time-Out (MTO) procedure
’LTD’ supported
Coefficients are no more retrievable by MON-8 commands
logic symbol, pin conf., pin definitions: removed TP1, MTO
49, 53: no function, may be clamped to GND or VDD, respectively,
for compatibility to former versions
added DELIC-PB, restriction on DELIC-PB, added Vbat, removed
solution with ELIC/IDEC (IDEC is discontinued)
added note on CLOCK and FSC from same source
added connection between pin CLOCK and FSC
changed: pins CLS 0..3 indicate 1 ms clock of the received frame.
added footnote to PU/PD to TCK in case that JTAG is reset: e.g.
pull-down 47 k
removed from all PD/PU-pins: internal pullup (160 k ), added
removed from PUP: (as soon as 1.FSC was received after reset)
updated pinning changes
added new table ’pin controlled test modes’
removed dedicated block diagram
replaced double last look criterion by real reaction times
removed MON0 commands
removed MTO function
NOP is always set to one
added note: activation of the interface to the analog front end
footnote to PU/PD: e.g. 10 to 20 k
2002-09-30
Preliminary Data Sheet, DS1, 6.99
3
DS1, 2002-09-30
PEF 24901
DS1
DFE-T