PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 24

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

2.2
Table 1
Pin No.
IOM
13
12
14
15
Mode Selection Pins
60
55
Data Sheet
®
-2 Interface
Pin Definitions and Functions
Pin Definitions and Functions
Symbol
FSC
DCL
DIN
DOUT
RES
SLOT0
Input (I)
Output (O)
I
I
I
O
(OD/PuP)
I
I
Frame Synchronization Clock (8 kHz)
Function
the start of the first B1-channel in time-slot 0 is
marked,
FSC is expected to be ’1’ for at least two DCL
periods.
Data Clock
clock rate ranges from 2048 to 8192 kHz
(1024 to 4096 kBit/s)
Data In
input of IOM
clock
Data Out
output of IOM
clock
Reset
triggers asynchronous HW reset, Schmitt
trigger input
’1’= inactive
’0’= active
(see
IOM
assigns IOM
SLOT1, 0:
’00’= IOM
’01’= IOM
’10’= IOM
’11’= IOM
25
®
Table
-2 Channel Slot Selection 0
®
®
®
®
-2 channels 0 to 3
-2 channels 4 to 7
-2 channels 8 to 11
-2 channels 12 to 15
3)
®
®
-2 data synchronous to DCL
®
-2 channels in blocks of 4
-2 data synchronous to DCL
Pin Descriptions
PEF 24901
2002-09-30
DFE-T