PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 42

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

The 4B3T data is coded with the bits TD1, TD0:
Table 6
4B3T Data Pulse
0
+ 1
– 1
The data on SDR is interpreted as follows:
LD:
SY:
Note: After reset , the interface to the analog frontend is activated with reception of FSC
Data Sheet
clock. If after activation the FSC is no more delivered, the interface to the analog
front end keeps running.
The level detect information is communicated to the DFE-T V2.2 on SDR.
If the signal amplitude reaches the wake-up level, the LD bit toggles with
the signal frequency. If the input signal at the U-interface is below the
wake-up level, the LD bit is tied to either low or high.
First bit of the time-slots with transmission data. For synchronization and bit
allocation on SDX, SY is set to ’1’ on SDX and ’0’ on SDR.
Coding of the 4B3T Data Pulse (AOUT/BOUT)
TD1
0
1
1
43
TD0
0
0
1
Functional Description
PEF 24901
2002-09-30
DFE-T