PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 30

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

2.3
Table 2
Pin No.
29, 20, 52, 61
32
45
49
53
55
56
62
63
Pin-Controlled Test Modes
Table 3
Mode
Reset (Master Reset)
Data-Through
Send-Single-Pulses
Undefined
Data Sheet
PuP: Push Pull
OD: Open Drain
PD: Internal Pull Down (e.g. 10 to 20 k )
PU: Internal Pull Up (e.g. 10 to 20 k )
Pinning Changes from DFE-T V1.2 to DFE-T V2.2
Pinning Changes
Pin Controlled Test Modes with DFE-T V2.2
V2.2
CLS0, 1, 2, 3 CLS0 1, 2, 3
PUP
SLOT1
N.C.
N.C.
SLOT0
SSP
DT
TRST
RES Pin
0
1
1
1
V1.2
SLOT2
N.C.
TP3
LT
SLOT
TSP
TP2
TP1
31
SSP Pin
don’t care
0
1
1
Comment
Clock of 1 ms Period to indicate
the received frame of Port 0, 1, 2,
3 (before: 120 kHz Transmit Baud
Clock)
additional push-pull mode for pin
DOUT eases interface adaption,
SLOT2 was not used in V1.2
increased max data rate (4 MBit/s)
requires an additional SLOT pin
no function
supported in V2.2
renamed
dedicated pin for ’Send Single
Pulses’ test mode
dedicated pin for ’Data Through’
test mode
power-on-reset is replaced by a
dedicated reset line
as in V1.x LT-RP mode is neither
Pin Descriptions
DT Pin
don’t care
1
0
1
PEF 24901
2002-09-30
DFE-T