PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 95

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

6.2.4
The Bit Error Rate Counter register contains the number of bit errors that occurred during
the period the bit TEST.BER was set active. If the low-significant register is read out the
BERC register is automatically reset to ’0’
BERC
Reset value: 0000
6.2.5
The Line Port Selection register selects the register bank that is associated with the
addressed line port. All line port specific register operations - line port specific registers
are indicated by a ’4’ in the last column of the register summary - are performed on the
line port that is addressed by the value of LP_SEL.
LP_SEL
Reset value: 00
LN2,1
Data Sheet
15
7
7
0
BERC - Bit Error Rate Counter Register
LP_SEL - Line Port Selection Register
Line Port Number
00 =
01 =
10 =
11 =
H
H
14
6
6
0
Line port no. 0 is addressed by the following command
Line port no. 1 is addressed by the following command
Line port no. 2 is addressed by the following command
Line port no. 3 is addressed by the following command
13
5
5
0
Bit Error Rate Counter Value
Bit Error Rate Counter Value
read/write
12
4
4
0
read
96
11
3
3
0
10
2
2
0
Register Description
LN2
Address: 13-14
9
1
1
Address: 1C
PEF 24901
2002-09-30
DFE-T
LN1
8
0
0
H
H