PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 41

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

The status on SDR is synchronized to SDX. Each time-slot on SDR carries the
corresponding LD bit during the last 12 bits of the slot.
Figure 13
The data on SDX is interpreted as follows:
NOP:
PDOW:
RANGE:
LOOP:
SY:
"0":
Data Sheet
The NOP bit is always set to ’1’.
If the PDOW bit is set to ’1’, the assigned line port is switched to power
down. Otherwise it is switched to power-up.
RANGE = ’1’ activates the range function, otherwise the range function is
deactivated. "Range function activated" refers to high input levels.
LOOP = ’1’ activates the loop function, i.e. the loop is closed. Otherwise the
line port is in normal operation.
First bit of the time-slots with transmission data. For synchronization and bit
allocation on SDX, SY is set to ’1’ on SDX and ’0’ on SDR.
Reserved bit. Reserved bits are currently not defined and shall be set to ’0’.
Some of these bits may be used for test purposes or can be assigned a
function in later versions.
Frame Structure on SDX/SDR
42
Functional Description
PEF 24901
2002-09-30
DFE-T