PEF24901HV22XT Lantiq, PEF24901HV22XT Datasheet - Page 64

• Manufacturer Part Number: PEF24901HV22XT
• Manufacturer: Lantiq

Specifications of PEF24901HV22XT

• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

DFE-T
PEF 24901
Functional Description
3.6
Clock Generation
The U-transceiver has to synchronize onto an externally provided PTT-master clock. A
phase locked loop (PLL) is integrated in the AFE (PEF 24902) to generate the 15.36 MHz
system clock. A synchronized system clock guarantees that U-interface transmission will
be synchronous to the PTT-master clock.
The AFE is able to synchronize onto a 8 kHz or a 2048 kHz system clock. Infineon
recommends to feed the FSC clock input of the DFE-T V2.2 and the PLL reference
clock input (pin CLOCK) of the AFE from the same clock source. Please refer to the
PEF 24902 Data Sheet for further details on the PLL.
For the connection of the AFE clock output line with the DFE-T V2.2 clock input line
(CL15) please refer to
Figure 4
and
Figure
5.
Data Sheet
65
2002-09-30