PEB2256H-V12 Infineon Technologies, PEB2256H-V12 Datasheet - Page 182
PEB2256H-V12
Manufacturer Part Number
PEB2256H-V12
Description
IC INTERFACE LINE 3.3V 80-MQFP
Manufacturer
Infineon Technologies
Datasheet
1.PEB2256H-V12.pdf
(490 pages)
Specifications of PEB2256H-V12
Applications
*
Interface
*
Voltage - Supply
*
Package / Case
80-SQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEB2256H-V12
PEB2256H-V12IN
PEB2256H-V12IN
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
PEB2256H-V12
Manufacturer:
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Quantity:
10 000
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5.6
5.6.1
The FALC56 has the added ability to generate and monitor a 2
Random Binary Sequences (PRBS). The generated PRBS pattern is transmitted to the
remote end on pins XL1/2 or XDOP/N and can be inverted optionally. Generating and
monitoring of PRBS pattern is done according to ITU-T O.151 and TR62411 with
maximum 14 consecutive zero restriction.
The PRBS monitor senses the PRBS pattern in the incoming data stream.
Synchronization is done on the inverted and non-inverted PRBS pattern. The current
synchronization status is reported in status and interrupt status registers. Enabled by bit
LCR1.EPRM each PRBS bit error increments an error counter (BEC). Synchronization
is reached within 400 ms with a probability of 99.9% and a bit error rate of up to 10
The PRBS generator and monitor can be used to handle either a framed
(TPC0.FRA = 1) or an unframed (TPC0.FRA = 0) data stream.
5.6.2
In the remote loop-back mode the clock and data recovered from the line inputs RL1/2
or RDIP/RDIN are routed back to the line outputs XL1/2 or XDOP/XDON through the
analog or digital transmitter. As in normal mode they are also processed by the
synchronizer and then sent to the system interface.The remote loop-back mode is
selected by setting the corresponding control bits LIM1.RL+JATT. Received data is
looped with or without use of the transmit jitter attenuator (FIFO).
Figure 72
Data Sheet
RL1
RL2
XL1
XL2
XCLK
Test Functions (T1/J1)
Pseudo-Random Binary Sequence Generation and Monitor
Remote Loop
Remote Loop (T1/J1)
Clock +
Data
Recovery
MUX
MUX
RCLK
RCLK
DCO-R/X
FIFO
182
Rec.
Framer
Trans.
Framer
Functional Description T1/J1
15
Elast.
Store
Elast.
Store
-1 and 2
FALC56 V1.2
ITS09750
20
PEB 2256
RDO
XDI
-1 Pseudo-
2002-08-27
-1
.
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